cpu/esp32: fix RISC-V ISA for ESP32-C3 with GCC 12.2

RIOT-OS · Oct 1, 2023 · 9a49dcd · 9a49dcd
1 parent 1ac1693
commit 9a49dcd
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/cpu/esp32/Makefile.include b/cpu/esp32/Makefile.include
@@ -241,7 +241,8 @@ CFLAGS += -D_CONST=const
 
 # TODO no relaxation yet
 ifneq (,$(filter riscv%,$(TARGET_ARCH)))
-  CFLAGS += -mno-relax -march=rv32imc -mabi=ilp32 -DRISCV_NO_RELAX
+  CFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32 -DRISCV_NO_RELAX
+  LINKFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32
   GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
                                $(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
                                                   -misa-spec=2.2 -E - > /dev/null 2>&1 && \