This repository contains a list of sample board designs for Libero. The sample designs contain Libero projects for FPGA designs including a RISC-V soft processor with programming bitstreams that can be used to program hardware using FlashPro Express. Select the hardware platform and follow instructions on it's page to implement it.
- Check this repository for updates on regular basis.
- Ensure you always have the latest Cores downloaded in Libero.
- Develop branch contains latest updates, master branch contains releases.
- If you have any queries be sure to check the F.A.Q's page in the repository
- Select one of the sample board designs from the list below by clicking on it's name.
- Download or Clone the selected repository, extract it wherever you want your Libero project built.
- Follow the instructions on the project's page to implement the design, ensure your version of Libero matches the version for which the scripts are written.
This is Microsemi's PolarFire FPGA Evaluation Kit. Information like data sheets, guides and support for this board can be found by clicking here, Microsemi's website. Below is an image of the board.
- The frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- FPGA: MPF300T or MPF300T_ES
- A soft RISC-V processor
This is the Future Avalanche Board for PolarFire FPGA - AVMPF300TS_01. Information like data sheets, guides and support for this board can be found by clicking here, Microsemi's website. A Libero Gold license is required to use the PolarFire part.
- The operational clock frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- A soft RISC-V processor
This is Microsemi's PolarFire Splash Kit board for evaluation and development. Information like data sheets, guides and support for this board can be found by clicking here, Microsemi's website. Below is an image of the board.
- The frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- This is project is marked 'ES' for Engineering Sample
- A soft RISC-V processor
This is an Arrow Everest Evaluation Board for PolarFire FPGA. Information like data sheets, guides and support for this board can befound by clicking here, Microsemi's website. Below is an image of the board.
- The frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- This is project is marked 'ES' for Engineering Sample
- A soft RISC-V processor
This is a Future designed IGLOO2 RISC-V Creative Development Board for IGLOO2 FPGA - FUTUREM2GL_EVB. Information like data sheets, guides and support for this board can be found by clicking here, Microsemi's website. Below is an image of the board.
- The frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- This board can come in colors: red, yellow or blue
- A soft RISC-V processor
This board is a SmartFusion2 Advanced Development Kit - SoC FPGA 150K LE - M2S150TS_ADV_DEV_KIT. Information like data sheets, guides and support for this board can be found by clicking here, Microsemi's website. Below is an image of the board.
- The frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- FPGA: M2S150 or M2S150TS
- A soft RISC-V processor
This is a Radiation-Tolerant High-Density High-Performance Development Board with one RT4G150 FPGA. Information like data sheets, guides and support for this board can be found by clicking here, Microsemi's website. Below is an image of the board
- The frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- A soft RISC-V processor
This is a SmartFusion2 Security Evaluation Kit - SoC FPGA 90K LE. Information like data sheets, guides and support for this board can be found by clicking here, Microsemi's website. Below is an image of the board.
- The frequency of the design is 50 MHz
- Latest cores have been implemented
- LSRAM for data and memory initialization
- FPGA: M2S090 or M2S090TS
- A soft RISC-V processor