Merge pull request #8 from someshd7/master

RTG4-Development-Kit Pull request Reviewed and accepted
RISCV-on-Microsemi-FPGA · Aug 31, 2018 · 7bd84a2 · 7bd84a2
2 parents 87a139d + 3de6ca2
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diff --git a/Modify_The_FPGA_Design/MIV_RV32IMA_BaseDesign_vlog.zip b/Modify_The_FPGA_Design/MIV_RV32IMA_BaseDesign_vlog.zip
diff --git a/Modify_The_FPGA_Design/MIV_RV32IMA_BaseDesign_vlog/MIV_RV32IMA_BaseDesign_vlog.prjx b/Modify_The_FPGA_Design/MIV_RV32IMA_BaseDesign_vlog/MIV_RV32IMA_BaseDesign_vlog.prjx
diff --git a/...Design/MIV_RV32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREABC/3.6.100/COREABC.cxf b/...Design/MIV_RV32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREABC/3.6.100/COREABC.cxf
diff --git a/...n/MIV_RV32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREABC/3.6.100/coreparameters.v b/...n/MIV_RV32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREABC/3.6.100/coreparameters.v
diff --git a/..._RV32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREAHBLSRAM/2.2.104/COREAHBLSRAM.cxf b/..._RV32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREAHBLSRAM/2.2.104/COREAHBLSRAM.cxf
diff --git a/...aseDesign_vlog/component/Actel/DirectCore/COREAHBLSRAM/2.2.104/mti/scripts/compileList.do b/...aseDesign_vlog/component/Actel/DirectCore/COREAHBLSRAM/2.2.104/mti/scripts/compileList.do
diff --git a/...V32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREAHBLSRAM/2.2.104/mti/scripts/run.do b/...V32IMA_BaseDesign_vlog/component/Actel/DirectCore/COREAHBLSRAM/2.2.104/mti/scripts/run.do