restore assertion and rejection

ROCm · Jan 14, 2025 · 8ae1a10 · 8ae1a10
1 parent a0ff71e
commit 8ae1a10
Show file tree

Hide file tree

Showing 2 changed files with 5 additions and 6 deletions.
diff --git a/tensilelite/Tensile/KernelWriterAssembly.py b/tensilelite/Tensile/KernelWriterAssembly.py
@@ -3540,8 +3540,7 @@ def lwaFirstOffset(self, kernel, tP):
       else:
         validBytesPerLoad *= (kernel["MacroTile%s"%tc] // kernel["NumLoadsPerpendicular%s"%tc] // (kernel["NumThreads"] // kernel["WavefrontSize"]))
 
-    # TODO- swizzling
-    # assert (validBytesPerLoad <= maxBytesPerLoad)
+    assert (validBytesPerLoad <= maxBytesPerLoad)
     assert (kernel[tP["lsc"]] * kernel[tP["lsp"]] % tP["glvw"] == 0)
 
     if validBytesPerLoad != maxBytesPerLoad:

diff --git a/tensilelite/Tensile/SolutionStructs.py b/tensilelite/Tensile/SolutionStructs.py
@@ -1412,10 +1412,10 @@ def setGlobalReadVectorWidth(state, tc, totalVectors, grvw):
     validDepthU = True
     if grvw not in [1,2,4,8,16,32]:
       validDepthU = False
-    # if totalVectors % state["NumThreads"] != 0:
-    #   reject(None, "totalVectors%s %u %% NumThreads %u != 0" \
-    #       % (tc, totalVectors, state["NumThreads"]))
-    #   validDepthU = False
+    if totalVectors % state["NumThreads"] != 0:
+      reject(None, "totalVectors%s %u %% NumThreads %u != 0" \
+          % (tc, totalVectors, state["NumThreads"]))
+      validDepthU = False
 
     state["GlobalReadVectorWidth%s"%tc] = grvw