added core_array code and activation function code #185

zymeng3001 · 2024-06-13T21:20:21Z

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…ructured packets of data used in different parts of the system

element-wise floating-point addition of two input data sets using pipeline

This module defines a parameterized global SRAM with configurable data width and depth, handling read and write operations using clock, address, and control signals. It instantiates a single-port memory (mem_sp) to perform the actual memory operations.

This module implements a clock divider that progressively divides an input clock signal by powers of two, from 2 up to 2048, with each divided clock driving the next stage.

This PLL module outputs a clock signal, clk_out, based on a 4-bit input configuration clk_cfg. The output clock is set to 1 if any of the configuration bits are high; otherwise, it is set to 0.

This Verilog module defines a controller for managing operations such as memory access, vector engine operations, and dataflow within a system, handling components like weight loading, attention mechanisms, and compute logic for Q, K, and V generations. It uses multiple finite state machines, counters, and control signals to manage the data flow between memory, global SRAM, and buffers, coordinating the execution of tasks across various stages of nanoGPT.

The current controller improves memory and buffer usage by limiting connections to necessary cores, optimizing Q write-back across different SRAMs, and disabling the ping-pong mechanism for residual paths. Additionally, it introduces more efficient attention operations with refined counters and interleaving logic to enhance data reuse and parallelism across heads during computation.

controller_bak.sv uses fixed values for parameters like CORE_ADDR_CNT and ABUF_CNT, while the earlier controllers calculate these dynamically. Additionally, controller_bak.sv has more detailed FSM logic and counter management, especially for handling QGEN, KGEN, VGEN, and attention operations

Module for SPI master functionality, handling data transmission as the master device.

SPI_SLAVE_TOP.sv: Top-level module for SPI slave, integrating various slave components. SPI_Slave.v: Module for the core functionality of an SPI slave. SPI_Slave_org.v: Original version of the SPI slave module, possibly kept for reference or testing. SPI_TOP_QIRUI.sv: Top-level module for the SPI system, integrating both master and slave components.

zymeng3001 added 30 commits June 3, 2024 16:11

Create core_top.v

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Add files via upload

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Create core_tb.sv

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Add files via upload

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Add files via upload

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Merge branch 'ReaLLMASIC:master' into master

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2D array for GEMM/GEMV with read, write and reset

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Floating-point division by 2

a79e187

Floating-point division by 4

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Floating-point division by 2

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Floating-point division by 4

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Floating-point GELU calculation unit

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Floating-point RELU calculation unit

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Floating-point SILU calculation unit

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empty layer_norm module

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Core structure

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align series to parallel

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counter without delay

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core activation buffer

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Delete HW/comp/vector_engine/activation/tb directory

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Delete HW/comp/vector_engine/consmax/tb directory

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Delete HW/comp/vector_engine/elementwise_add/rtl directory

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Delete HW/comp/vector_engine/softermax directory

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Delete HW/comp/vector_engine/softmax directory

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Delete HW/comp/util/sim directory

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Delete HW/comp/util/tb directory

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Define array dimensions, data widths, memory depths, and types for st…

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…ructured packets of data used in different parts of the system

Delete HW/comp/core_array/tb directory

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Delete HW/comp/core_fake_mem/tb directory

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list file used by synthesis, simulation

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zymeng3001 added 30 commits September 16, 2024 02:04

Create elem_fp_add.v

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element-wise floating-point addition of two input data sets using pipeline

Create define.vh

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Create vector_engine_README.md

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Create core_acc.v

ca81736

Rename HW/comp/core/core_acc.v to HW/comp/core/rtl/core_acc.v

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Create core_buf.v

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Create core_mac.v

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Create core_mem.v

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Create core_quant.v

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Create core_top.lst

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Create core_top.v

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Update core_array_README.md

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Create core_README.md

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Create gloobal_sram.sv

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This module defines a parameterized global SRAM with configurable data width and depth, handling read and write operations using clock, address, and control signals. It instantiates a single-port memory (mem_sp) to perform the actual memory operations.

Create clk_div.sv

08d401b

This module implements a clock divider that progressively divides an input clock signal by powers of two, from 2 up to 2048, with each divided clock driving the next stage.

Create pll.sv

ed2e1cf

This PLL module outputs a clock signal, clk_out, based on a 4-bit input configuration clk_cfg. The output clock is set to 1 if any of the configuration bits are high; otherwise, it is set to 0.

Create controller.lst

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Create controller_testbench.sv

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Create controller_top_testbench.sv

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Create controller_att_testbench.sv

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Create core_tb.sv

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Create SPI_DEF.svh

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Add SPI_Master.v

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Module for SPI master functionality, handling data transmission as the master device.

Create fexp.v

b010cc2

Create fexp_tb.v

1ab8f4b

Create fexp.v

e60fd29

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added core_array code and activation function code #185

added core_array code and activation function code #185

zymeng3001 commented Jun 13, 2024

added core_array code and activation function code #185

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added core_array code and activation function code #185

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zymeng3001 commented Jun 13, 2024