MPEG1_VIDEO_COMPRESSION

Overview

This work has beed done by ECE students at Cal Poly Pomona as a collaboration with Xilinx on developing an MPEG-1 Compression Algorithm on a Pynq-z1 FPGA board. The goal of this project was to compare the compression algorithm using both Verilog and Python code. The comparison includes observing the performance metrics on both experiments and concluding which code is more appropriate in different situations.

Team Members:

1. Lucky Douangmanivong: Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.
2. Ryan White: Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.
3. Trey Nguyen: Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.
4. Jaehyun Kim: Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.
5. Jaime Castro:Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.
6. Eric Ly: Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.

Supervising Professor:

• Mohamed El-Hadedy: Assistant Professor, Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.

• Anas Salah Eddin: Assistant Professor, Electrical and Computer Engineering department, College of Engineering, California State Polytechnic University, Pomona.

Official Presentation by the group:

https://youtu.be/S8GB3TAaYwY

Project Sponsors:

1. Xilinx Inc.