Skip to content

Commit

Permalink
Revert "[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (llvm#1…
Browse files Browse the repository at this point in the history
…19461)"

This reverts commit 169c32e.
  • Loading branch information
MaheshRavishankar authored and DavidGinten committed Jan 22, 2025
1 parent 0bdbc1c commit 201629f
Show file tree
Hide file tree
Showing 2 changed files with 539 additions and 1 deletion.
3 changes: 3 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Original file line number Diff line number Diff line change
Expand Up @@ -781,10 +781,12 @@ define void @copysign_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -1203,6 +1205,7 @@ define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addi a2, a1, -1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v9
; CHECK-NEXT: vxor.vx v9, v10, a1
Expand Down
Loading

0 comments on commit 201629f

Please sign in to comment.