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Added site styling changes for ApexCore
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RapidRoger18 committed May 15, 2024
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7 changes: 3 additions & 4 deletions _projects/ApexCore.md
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| Project Domains | Mentors | Project Difficulty |
|----------------------------------------------|---------------------------------|--------------------|
| Computer Architecture, FPGA, Degital Design | Atharva Kashalkar, Saish Karole | Hard |
| Computer Architecture, FPGA, Digital Design | Atharva Kashalkar, Saish Karole | Hard |
<br>

### Project Description
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SRA hosts its own 32-bit RISC-V Core, supporting the IM extensions. Currently compatible with an open-source toolchain, our core is poised for greater versatility.<br>
This project aims to integrate our RISC-V core into the Xilinx Vivado ecosystem, allowing users to effortlessly drag and drop it into their designs as a soft core. Additionally, we aim to rigorously verify the RISC-V core using industry-standard methods for testing digital designs. Ensuring the core's reliability and performance will provide a robust solution for a wide range of applications.

This integration will significantly expand the use cases for SRA’s RISC-V core. By leveraging the peripherals and IPs compatible with Xilinx boards, users will be able to design custom SoCs centered around our powerful RISC-V core. This initiative opens up exciting possibilities for innovative and efficient custom solutions.

### Resources

[Inside a CPU](https://www.youtube.com/watch?v=IAkj32VPcUE)<br>
[What is Risc-V?](https://www.youtube.com/watch?v=Ps0JFsyX2fU)<br>
[What is a FPGA](https://www.youtube.com/watch?v=WY-F3knih7c)<br>
[MicroBlaze Processor](https://www.xilinx.com/products/design-tools/microblaze.html).
[MicroBlaze Processor](https://www.xilinx.com/products/design-tools/microblaze.html)<br>
[Verification of a CPU](https://www.youtube.com/watch?v=Hg3O4Ti92gk)
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289 changes: 289 additions & 0 deletions _site/projects/ApexCore/index.html
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<!DOCTYPE html>
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<title>ApexCore a Risc-V based CPU | Eklavya 2024 </title>
<meta name="author" content="Eklavya 2024 ">
<meta name="description" content="Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.">
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<header class="post-header">
<h1 class="post-title">ApexCore a Risc-V based CPU</h1>
<p class="post-description">Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.</p>
</header>

<article>
<table>
<thead>
<tr>
<th>Project Domains</th>
<th>Mentors</th>
<th>Project Difficulty</th>
</tr>
</thead>
<tbody>
<tr>
<td>Computer Architecture, FPGA, Digital Design</td>
<td>Atharva Kashalkar, Saish Karole </td>
<td>Hard</td>
</tr>
</tbody>
</table>
<p><br></p>

<h3 id="project-description">Project Description</h3>

<p>SRA hosts its own 32-bit RISC-V Core, supporting the IM extensions. Currently compatible with an open-source toolchain, our core is poised for greater versatility.<br>
This project aims to integrate our RISC-V core into the Xilinx Vivado ecosystem, allowing users to effortlessly drag and drop it into their designs as a soft core. Additionally, we aim to rigorously verify the RISC-V core using industry-standard methods for testing digital designs. Ensuring the core’s reliability and performance will provide a robust solution for a wide range of applications.</p>

<h3 id="resources">Resources</h3>

<p><a href="https://www.youtube.com/watch?v=IAkj32VPcUE" rel="external nofollow noopener" target="_blank">Inside a CPU</a><br>
<a href="https://www.youtube.com/watch?v=Ps0JFsyX2fU" rel="external nofollow noopener" target="_blank">What is Risc-V?</a><br>
<a href="https://www.youtube.com/watch?v=WY-F3knih7c" rel="external nofollow noopener" target="_blank">What is a FPGA</a><br>
<a href="https://www.xilinx.com/products/design-tools/microblaze.html" rel="external nofollow noopener" target="_blank">MicroBlaze Processor</a><br>
<a href="https://www.youtube.com/watch?v=Hg3O4Ti92gk" rel="external nofollow noopener" target="_blank">Verification of a CPU</a></p>

</article>

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max: getDistanceToScroll(),
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<meta http-equiv="X-UA-Compatible" content="IE=edge">
<title>GyroGlider | Eklavya 2024 </title>
<meta name="author" content="Eklavya 2024 ">
<meta name="description" content="Implementing Self Balancing on SRA's latest morphable bot-EvoBourne in a semi-drone mode.">
<meta name="description" content="Implementing Self Balancing on SRA's latest morphable bot-EvoBorne in a semi-drone mode.">
<meta name="keywords" content="jekyll, jekyll-theme, academic-website, portfolio-website">


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<link rel="shortcut icon" href="/assets/img/favicon.ico">

<link rel="stylesheet" href="/assets/css/main.css">
<link rel="canonical" href="http://localhost:4000/projects/Evobourne/">
<link rel="canonical" href="http://localhost:4000/projects/GyroGlider/">

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<header class="post-header">
<h1 class="post-title">GyroGlider</h1>
<p class="post-description">Implementing Self Balancing on SRA's latest morphable bot-EvoBourne in a semi-drone mode.</p>
<p class="post-description">Implementing Self Balancing on SRA's latest morphable bot-EvoBorne in a semi-drone mode.</p>
</header>

<article>
Expand Down Expand Up @@ -144,7 +144,7 @@ <h3 id="project-description">Project Description</h3>

<p>The ultimate goal? EvoBorne will have a semi-drone mode, allowing it to navigate any environment with ease. This semi-drone capability represents a significant step forward in the evolution of robotics, promising seamless and agile movement across all types of challenging terrain. By use of cutting-edge technologies like SLAM (Simultaneous Localization and Mapping) and advanced trajectory planning EvoBorne bot will achieve full autonomy to traverse through its environment. This is the exciting vision driving the development of EvoBorne.</p>

<p><img src="/assets/img/Morphobot-SB.png" alt="Morphobot-SB.png"></p>
<p><img src="/assets/gifs/M4-SB.gif" alt="M4-SB.gif"></p>

<h3 id="resources">Resources</h3>
<p><a href="https://www.youtube.com/watch?v=YfeBMIqmg1o" rel="external nofollow noopener" target="_blank">M4 by CalTech</a> <br>
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