[PROJECT]: Adds ApexCore project to final list #203
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| title: ApexCore a Risc-V based CPU | ||
| description: Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards. | ||
| importance: 1 | ||
| --- | ||
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| | Project Domains | Mentors | Project Difficulty | | ||
| |----------------------------------------------|---------------------------------|--------------------| | ||
| | Computer Architecture, FPGA, Digital Design | Atharva Kashalkar, Saish Karole | Hard | | ||
| <br> | ||
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| ### Project Description | ||
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| SRA hosts its own 32-bit RISC-V Core, supporting the IM extensions. Currently compatible with an open-source toolchain, our core is poised for greater versatility.<br> | ||
| This project aims to integrate our RISC-V core into the Xilinx Vivado ecosystem, allowing users to effortlessly drag and drop it into their designs as a soft core. Additionally, we aim to rigorously verify the RISC-V core using industry-standard methods for testing digital designs. Ensuring the core's reliability and performance will provide a robust solution for a wide range of applications. | ||
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| ### Resources | ||
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| [Inside a CPU](https://www.youtube.com/watch?v=IAkj32VPcUE)<br> | ||
| [What is Risc-V?](https://www.youtube.com/watch?v=Ps0JFsyX2fU)<br> | ||
|
There was a problem hiding this comment. Change this and more instances of Risc-V to RISC-V. |
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| [What is a FPGA](https://www.youtube.com/watch?v=WY-F3knih7c)<br> | ||
| [MicroBlaze Processor](https://www.xilinx.com/products/design-tools/microblaze.html)<br> | ||
| [Verification of a CPU](https://www.youtube.com/watch?v=Hg3O4Ti92gk) | ||
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| <title>ApexCore a Risc-V based CPU | Eklavya 2024 </title> | ||
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| <meta name="description" content="Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards."> | ||
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| <h1 class="post-title">ApexCore a Risc-V based CPU</h1> | ||
| <p class="post-description">Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.</p> | ||
| </header> | ||
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| <article> | ||
| <table> | ||
| <thead> | ||
| <tr> | ||
| <th>Project Domains</th> | ||
| <th>Mentors</th> | ||
| <th>Project Difficulty</th> | ||
| </tr> | ||
| </thead> | ||
| <tbody> | ||
| <tr> | ||
| <td>Computer Architecture, FPGA, Digital Design</td> | ||
| <td>Atharva Kashalkar, Saish Karole </td> | ||
| <td>Hard</td> | ||
| </tr> | ||
| </tbody> | ||
| </table> | ||
| <p><br></p> | ||
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| <h3 id="project-description">Project Description</h3> | ||
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| <p>SRA hosts its own 32-bit RISC-V Core, supporting the IM extensions. Currently compatible with an open-source toolchain, our core is poised for greater versatility.<br> | ||
| This project aims to integrate our RISC-V core into the Xilinx Vivado ecosystem, allowing users to effortlessly drag and drop it into their designs as a soft core. Additionally, we aim to rigorously verify the RISC-V core using industry-standard methods for testing digital designs. Ensuring the core’s reliability and performance will provide a robust solution for a wide range of applications.</p> | ||
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| <h3 id="resources">Resources</h3> | ||
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| <p><a href="https://www.youtube.com/watch?v=IAkj32VPcUE" rel="external nofollow noopener" target="_blank">Inside a CPU</a><br> | ||
| <a href="https://www.youtube.com/watch?v=Ps0JFsyX2fU" rel="external nofollow noopener" target="_blank">What is Risc-V?</a><br> | ||
| <a href="https://www.youtube.com/watch?v=WY-F3knih7c" rel="external nofollow noopener" target="_blank">What is a FPGA</a><br> | ||
| <a href="https://www.xilinx.com/products/design-tools/microblaze.html" rel="external nofollow noopener" target="_blank">MicroBlaze Processor</a><br> | ||
| <a href="https://www.youtube.com/watch?v=Hg3O4Ti92gk" rel="external nofollow noopener" target="_blank">Verification of a CPU</a></p> | ||
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Replace
IM extensionswithRV32IM extension