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[MINOR UPDATE]: Adds styling changes for ApexCore Project #205

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merged 3 commits into from
May 16, 2024
Merged

[MINOR UPDATE]: Adds styling changes for ApexCore Project #205

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c804f77
Added site styling changes for ApexCore
RapidRoger18 May 16, 2024
626ca29
Added site styling changes for ApexCore
RapidRoger18 May 16, 2024
b1fda91
Merge branch 'SRA-VJTI:main' into RV-project
RapidRoger18 May 16, 2024
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5 changes: 3 additions & 2 deletions _projects/ApexCore.md
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@@ -1,13 +1,14 @@
---
layout: page
title: ApexCore a Risc-V based CPU
description: Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.
title: ApexCore a RISC-V based CPU
description: Developing a RISC-V based soft processor IP compatible with AMD's Xilinx Boards.
importance: 1
---

| Project Domains | Mentors | Project Difficulty |
|----------------------------------------------|---------------------------------|--------------------|
| Computer Architecture, FPGA, Digital Design | Atharva Kashalkar, Saish Karole | Hard |

<br>

### Project Description
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39 changes: 20 additions & 19 deletions _site/projects/ApexCore/index.html
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<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<meta http-equiv="X-UA-Compatible" content="IE=edge">
<title>ApexCore a Risc-V based CPU | Eklavya 2024 </title>
<title>ApexCore a RISC-V based CPU | Eklavya 2024 </title>
<meta name="author" content="Eklavya 2024 ">
<meta name="description" content="Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.">
<meta name="description" content="Developing a RISC-V based soft processor IP compatible with AMD's Xilinx Boards.">
<meta name="keywords" content="jekyll, jekyll-theme, academic-website, portfolio-website">


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<div class="post table-borderless">

<header class="post-header">
<h1 class="post-title">ApexCore a Risc-V based CPU</h1>
<p class="post-description">Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.</p>
<h1 class="post-title">ApexCore a RISC-V based CPU</h1>
<p class="post-description">Developing a RISC-V based soft processor IP compatible with AMD's Xilinx Boards.</p>
</header>

<article>
<table>
<thead>
<tr>
<th>Project Domains</th>
<th>Mentors</th>
<th>Project Difficulty</th>
</tr>
</thead>
<tbody>
<tr>
<td>Computer Architecture, FPGA, Digital Design</td>
<td>Atharva Kashalkar, Saish Karole </td>
<td>Hard</td>
</tr>
</tbody>
</table>
<thead>
<tr>
<th>Project Domains</th>
<th>Mentors</th>
<th>Project Difficulty</th>
</tr>
</thead>
<tbody>
<tr>
<td>Computer Architecture, FPGA, Digital Design</td>
<td>Atharva Kashalkar, Saish Karole</td>
<td>Hard</td>
</tr>
</tbody>
</table>

<p><br></p>

<h3 id="project-description">Project Description</h3>
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