Skip to content

RTL implementation of the AES algorithm with 128-bit key using Verilog.

Notifications You must be signed in to change notification settings

Shehab-Naga/AES-128

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

14 Commits
 
 
 
 
 
 
 
 
 
 

Repository files navigation

AES-128

This project is an RTL-based implementation of AES with a 128-bits key. It uses ten rounds for 128-bit keys. Each round comprises a series of operations as follows:

  • Byte substitution
  • Rows shifting
  • Matrix multiplication
  • Adding with a key specific for each round

About

RTL implementation of the AES algorithm with 128-bit key using Verilog.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published