This repository is a documentation of the RTL Design, Verification, and FPGA Implementation of an Elevator Controller project, which was part of my internship at PyramidTech during Summer 2022. The FPGA imprementation was done using Terasic DE0-CV development board and Intel Quartus Prime.
The project is divided into three parts:
- Part I is the RTL Design of the elevator using VHDL
- Part II is the verification of the design using self-checking testbenches and simulation
- Part III is the FPGA implementation and validation of the elevator controller on Terasic DE0-CV development board
The repository includes the following:
- RTL directory containing the design files (.vhd)
- Quartus directory containing Intel Quartus Prime files (.qsf, .qpf, and .sdc)
- Testbench directory containing the testbench files (.vhd), simulation script (.txt), and inputs and outputs files (.txt)
- In the main directory, there are the FPGA testing video (.mp4) and documentation report (.pdf)