Five-Stage-Pipelined MIPS Processor Verilog Implementation
Project Specification: https://pages.cs.wisc.edu/~sinclair/courses/cs552/spring2022/project.html
Final CPI = 5.286744
Project Grade:
Project Design Review: 4.69/5
Phase 1: 15/15
Phase 2: 27/27 + 3/3
Phase 2.3: 10/10
Phase 3: 25.5/25.5
CPI Ranking: 3 out of 52, 4.25/4.5
Extra Credit: 10/10 for
- Branch Decision in Decode stage
- Additional forwarding paths
- LRU cache replacement policy
- Exception Handling
- Synthesizing the design
- Critical Word First Read (LRU) Cache
Homework (sub-projects) Scores:
- HW1: 10/10
- HW2: 15/15
- HW3: 20/20
- HW4: 12/12
- HW5: 15.88/16