Update SiEPIC_EBeam_DRC.lydrc

klayout/EBeam/drc/SiEPIC_EBeam_DRC.lydrc

@@ -48,8 +48,8 @@ LayerDeepTrench=input(201,0)
 #################
 
 # Check device overlaps (functional check)
-overlaps = DevRec.merged(2)
-output(overlaps, "Devices","Devices cannot be overlapping")
+#overlaps = DevRec.merged(2)
+#output(overlaps, "Devices","Devices cannot be overlapping")
 
 # make sure the devices are within the floor plan layer region;
 LayerSi.outside(LayerFP).output("Boundary","devices are out of boundary")
@@ -63,7 +63,7 @@ tol = 1e-3  # users typically shoot for exactly the min features
             # for curves, this leads to lots of false errors.
 
 # minimum feature size of Si is 70 nm and minimum exclusion between Si is 70 nm
-LayerSi.width(0.07-tol, angle_limit(80)).output("Si_width","Si minimum feature size violation; min 60 nm")
+LayerSi.width(0.06-tol, angle_limit(80)).output("Si_width","Si minimum feature size violation; min 60 nm")
 #LayerSip6nm.width(0.07-tol, angle_limit(80)).output("Sip6nm_width","Si minimum feature size violation; min 60 nm")
 LayerSi.space(0.07-tol, angle_limit(80)).output("Si_space","Si minimum space violation; min 60 nm")
 #LayerSip6nm.space(0.07-tol, angle_limit(80)).output("Sip6nm_space","Si minimum space violation; min 60 nm")
@@ -121,8 +121,8 @@ LayerM2.overlap(LayerM1,3.0-tol).output("M2_M1_overlap","M2 minimum overlap with
 # Waveguide checks:
 # disconnects, mismatched
 
-PinRec.not_inside(LayerSi).and(PinRec.not_inside(LayerSiN))
-    .output( "SiEPIC-1a" , "Warning: Possible waveguide mismatch or waveguide disconnect: PinRec must enclose only one waveguide material." )
+#PinRec.not_inside(LayerSi).and(PinRec.not_inside(LayerSiN))
+#    .output( "SiEPIC-1a" , "Warning: Possible waveguide mismatch or waveguide disconnect: PinRec must enclose only one waveguide material." )
 
 LayerDeepTrench.separation(LayerM2, 20.0-tol).output("DT_Metal_separation","DT-Metal minimum separation violation; min 20 µm")</text>
 </klayout-macro>