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SiN GC loopback test. This layout has DRC errors: Connectivity: 'Disconnected pin' I generated this layout manually in KLayout. I used GC_SiN_TE_1550_8degOxide_BB GCs. I generated the waveguide connections using "Path to Waveguide" with the following settings: Configuration: SiN Strip TE 1550 nm, w=750nm (width matching the GC pin width) If the DRC errors are not nuisance errors, I'd appreciate feedback on how I can fix them.
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit. You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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It appears that there is a problem with the pins on the GC_SiN_TE_1550_8degOxide_BB GCs component. I see that EBeam_LukasChrostowski_MZI.py uses a 1310nm GC, ebeam_GC_SiN_TE_1310_8deg. Is there a working SiN 1550nm GC? |
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Cancelling |
SiN GC loopback test.
This layout has DRC errors:
Connectivity: 'Disconnected pin'
I generated this layout manually in KLayout. I used GC_SiN_TE_1550_8degOxide_BB GCs. I generated the waveguide connections using "Path to Waveguide" with the following settings: Configuration: SiN Strip TE 1550 nm, w=750nm (width matching the GC pin width)
If the DRC errors are not nuisance errors, I'd appreciate feedback on how I can fix them.