bad pull request -- will cancel #3
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This layout contains a set of loopbacks to characterize the GC_SiN_TE_1550_8degOxide_BB GC. However, this component has a pin issue. I believe this is the source of all the DRC issues with my layout.
Running functional verification ("V") on a layout with a single GC_SiN_TE_1550_8degOxide_BB component produces the following error:
Invalid Pin [TOP]
Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
polygon: (9.115,0.575;9.115,0.585;9.125,0.585;9.125,0.575)
The components with the pin problem is: GC_SiN_TE_1550_8degOxide_BB
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