upload of prelimenary design

[felme1]

This design aims to prove, that the network proposed in https://ieeexplore.ieee.org/document/9233963 does indeed work in the optical domain.

[felme1]

There are a few verification errors, that I do not think pose any problem, so I want to go through all of them here:
All four designs are quite similar, with the difference that the network that I want to test is altered to get different phase shifts at the respective stages in the network.

Component errors

Overlapping components

These errors occur because the components Waveguide_SBend and Waveguide_bump have bounding boxes that are larger than they should be. At no point in this layout are waveguides closer to each other than at the output of the Y-Branch.

Invalid Pin

These errors are due to the custom waveguide crossing that I have created, I am unsure why this is being shown as an error. But I have done a manual inspection and couldn't find any problems

Connectivity errors

I am unsure why this seems to be a problem. This occurs at the interfaces with the Wavguide_bump as well as my custom component. Upon manually inspecting the interfaces everything seems to be in order.

opt_in label missing

This problem occurs because the program doesn't realize that the ports on my custom component are internally connected, so it thinks that one of the grating couplers is not connected to the circuit.

[lukasc-ubc]

Nice design!

• Waveguide S-Bend: no need to use that component anymore. We added S-bends to the Waveguide cell. It will complain about the radius, but it works fine. It would be nice to remove the warning (which is useful if you draw something that really does violate the bend radius).

• Waveguide Bump: noted, and created an Issue in the EBeam PDK repo.

• Crossing -- there should only be one DevRec geometry per component. At least that is how we implemented it. Grow them, then Edit > Selection > Merge ... This resolves the invalid pin.

- May we add your crossings (I fixed the DevRec layers) into the EBeam PDK? I put them in this branch: https://github.com/SiEPIC/SiEPIC_EBeam_PDK/tree/crossings - did you simulate them? What is the insertion loss, and cross-talk? Did you consider extending the tapers to ensure they are adiabatic?

[felme1]

@lukasc-ubc thank you for the clarification. This crossing design was just a placeholder, so I could simualte the real one, but be sure that I get some space on the Chip. However my latest pull request contains a crossing that I have simulated in Lumerical FDTD.