Merge pull request #25 from SiLab-Bonn/github_actions_CI

Update simulation tests and use Github actions for CI

.github/workflows/tests.yml

@@ -0,0 +1,52 @@
+name: Software tests
+
+on: push
+
+jobs:
+  tests:
+    name: Test
+    runs-on: ubuntu-20.04
+    strategy:
+      fail-fast: false
+    steps:
+    - uses: actions/checkout@v2
+    - name: Set up Anaconda
+      uses: conda-incubator/setup-miniconda@v2
+      with:
+        auto-update-conda: true
+        python-version: 3.9
+    - name: Install Conda dependencies
+      shell: bash -l {0}
+      run: |
+        conda info -a
+        conda install pytest numpy psutil qtpy pyyaml pyzmq pytables
+    - name: Install basil
+      shell: bash -l {0}
+      run: |
+        pip install basil-daq>=3.0.0
+    - name: Install Python dependencies
+      shell: bash -l {0}
+      run: |
+        pip install cocotb cocotb_bus xvfbwrapper pyqt5
+    - name: Install iverilog
+      run: |
+        sudo apt-get install -qq libhdf5-serial-dev libxkbcommon-x11-0
+        sudo apt-get install '^libxcb.*-dev'
+        # sudo apt-get -y install iverilog-daily
+        sudo apt-get install gperf
+        git clone https://github.com/steveicarus/iverilog.git
+        cd iverilog; autoconf; ./configure; make; sudo make install; cd ..
+    - name: Install EUDAQ
+      shell: bash -l {0}
+      run: |
+        source tests/setup_eudaq.sh
+    - name: Install package
+      shell: bash -l {0}
+      run: |
+        pip install -e .
+    - name: Test
+      shell: bash -l {0}
+      run: |
+        cd tests
+        pytest -s -v
+

.gitignore

@@ -76,4 +76,6 @@ output_data
 *.lprof
 
 *.history
-.
+
+sim_build
+results.xml

firmware/src/tlu.v

@@ -15,8 +15,11 @@
 `include "utils/ddr_des.v"
 `include "utils/cdc_syncfifo.v"
 `include "utils/generic_fifo.v"
+`include "utils/ramb_8_to_n.v"
 
 `include "gpio/gpio.v"
+`include "gpio/gpio_core.v"
+
 
 `include "i2c/i2c.v"
 `include "i2c/i2c_core.v"

tests/StreamDriver.py

@@ -12,10 +12,9 @@
 
 import cocotb
 from cocotb.binary import BinaryValue
-from cocotb.triggers import RisingEdge, ReadOnly, Timer
-from cocotb.drivers import BusDriver
-from cocotb.result import ReturnValue
+from cocotb.triggers import RisingEdge, Timer
 from cocotb.clock import Clock
+from cocotb_bus.drivers import BusDriver
 
 
 class StreamDriver(BusDriver):
@@ -25,37 +24,37 @@ class StreamDriver(BusDriver):
     _optional_signals = ["BUS_BYTE_ACCESS"]
 
     def __init__(self, entity):
-        BusDriver.__init__(self, entity, "", entity.BUS_CLK)
+        BusDriver.__init__(self, entity, "", entity.BUS_CLK, case_insensitive=False)
 
         # Create an appropriately sized high-impedence value
-        self._high_impedence = BinaryValue(bits=len(self.bus.BUS_DATA))
+        self._high_impedence = BinaryValue(n_bits=len(self.bus.BUS_DATA))
         self._high_impedence.binstr = "Z" * len(self.bus.BUS_DATA)
 
         # Create an appropriately sized high-impedence value
-        self._x = BinaryValue(bits=len(self.bus.BUS_ADD))
+        self._x = BinaryValue(n_bits=len(self.bus.BUS_ADD))
         self._x.binstr = "x" * len(self.bus.BUS_ADD)
 
         self._has_byte_acces = False
 
         self.BASE_ADDRESS_STREAM = 0x0001000000000000
 
         # Kick off a clock generator
-        cocotb.fork(Clock(self.clock, 20830).start())
+        cocotb.fork(Clock(self.clock, 20000).start())
 
     @cocotb.coroutine
     def init(self):
         # Defaults
-        self.bus.BUS_RST <= 1
-        self.bus.BUS_RD <= 0
-        self.bus.BUS_WR <= 0
-        self.bus.BUS_ADD <= self._x
-        self.bus.BUS_DATA <= self._high_impedence
-        self.bus.STREAM_READY <= 0
+        self.bus.BUS_RST.value = 1
+        self.bus.BUS_RD.value = 0
+        self.bus.BUS_WR.value = 0
+        self.bus.BUS_ADD.value = self._x
+        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.STREAM_READY.value = 0
 
         for _ in range(8):
             yield RisingEdge(self.clock)
 
-        self.bus.BUS_RST <= 0
+        self.bus.BUS_RST.value = 0
 
         for _ in range(2):
             yield RisingEdge(self.clock)
@@ -75,20 +74,20 @@ def read(self, address, size):
         if address >= self.BASE_ADDRESS_STREAM:
             result = yield self.read_stream(address, size)
         else:
-            self.bus.BUS_DATA <= self._high_impedence
-            self.bus.BUS_ADD <= self._x
-            self.bus.BUS_RD <= 0
+            self.bus.BUS_DATA.value = self._high_impedence
+            self.bus.BUS_ADD.value = self._x
+            self.bus.BUS_RD.value = 0
 
             yield RisingEdge(self.clock)
 
             byte = 0
             while(byte <= size):
                 if(byte == size):
-                    self.bus.BUS_RD <= 0
+                    self.bus.BUS_RD.value = 0
                 else:
-                    self.bus.BUS_RD <= 1
+                    self.bus.BUS_RD.value = 1
 
-                self.bus.BUS_ADD <= address + byte
+                self.bus.BUS_ADD.value = address + byte
 
                 yield RisingEdge(self.clock)
 
@@ -113,38 +112,38 @@ def read(self, address, size):
                 else:
                     byte += 1
 
-            self.bus.BUS_ADD <= self._x
-            self.bus.BUS_DATA <= self._high_impedence
+            self.bus.BUS_ADD.value = self._x
+            self.bus.BUS_DATA.value = self._high_impedence
             yield RisingEdge(self.clock)
 
-        raise ReturnValue(result)
+        return result
 
     @cocotb.coroutine
     def write(self, address, data):
 
-        self.bus.BUS_ADD <= self._x
-        self.bus.BUS_DATA <= self._high_impedence
-        self.bus.BUS_WR <= 0
+        self.bus.BUS_ADD.value = self._x
+        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.BUS_WR.value = 0
 
         yield RisingEdge(self.clock)
 
         for index, byte in enumerate(data):
-            self.bus.BUS_DATA <= byte
-            self.bus.BUS_WR <= 1
-            self.bus.BUS_ADD <= address + index
+            self.bus.BUS_DATA.value = byte
+            self.bus.BUS_WR.value = 1
+            self.bus.BUS_ADD.value = address + index
             yield Timer(1)  # This is hack for iverilog
-            self.bus.BUS_DATA <= byte
-            self.bus.BUS_WR <= 1
-            self.bus.BUS_ADD <= address + index
+            self.bus.BUS_DATA.value = byte
+            self.bus.BUS_WR.value = 1
+            self.bus.BUS_ADD.value = address + index
 
             yield RisingEdge(self.clock)
 
         if(self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0):
             raise NotImplementedError("BUS_BYTE_ACCESS for write to be implemented.")
 
-        self.bus.BUS_DATA <= self._high_impedence
-        self.bus.BUS_ADD <= self._x
-        self.bus.BUS_WR <= 0
+        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.BUS_ADD.value = self._x
+        self.bus.BUS_WR.value = 0
 
         yield RisingEdge(self.clock)
 
@@ -153,7 +152,7 @@ def read_stream(self, address, size):
         result = []
 
         yield RisingEdge(self.clock)
-        self.bus.STREAM_READY <= 1
+        self.bus.STREAM_READY.value = 1
 
         for _ in range(size // 2):
 
@@ -169,8 +168,7 @@ def read_stream(self, address, size):
         yield RisingEdge(self.clock)
         yield RisingEdge(self.clock)
         yield RisingEdge(self.clock)
-        self.bus.STREAM_READY <= 0
+        self.bus.STREAM_READY.value = 0
         yield RisingEdge(self.clock)
 
-        raise ReturnValue(result)
-
+        return result

tests/test_Sim.py

@@ -25,7 +25,7 @@ def setUp(self):
             include_dirs=(root_dir, root_dir + "/firmware/src", root_dir + "/tests"))
 
         with open(root_dir + '/pytlu/tlu.yaml', 'r') as f:
-            cnfg = yaml.load(f)
+            cnfg = yaml.safe_load(f)
         cnfg['transfer_layer'][0]['type'] = 'SiSim'
         cnfg['hw_drivers'].append({'name': 'SEQ_GEN_TB', 'type': 'seq_gen', 'interface': 'intf', 'base_addr': 0xc000})
         cnfg['hw_drivers'].append({'name': 'TLU_TB', 'type': 'tlu', 'interface': 'intf', 'base_addr': 0xf000})
@@ -362,7 +362,7 @@ def test_tlu_veto(self):
         while not self.dut['test_pulser'].is_ready:
             pass
 
-        expected_vetoed_triggers = 29  # 29 triggers will not be accepted due to veto signal
+        expected_vetoed_triggers = 28  # 28 triggers will not be accepted due to veto signal
         self.check_data(how_many_triggers - expected_vetoed_triggers)
 
     def tearDown(self):