Fix esp32c3 FPU issues (#2700)

* Add various linker definitions From inspection of IDF makelists * Fix floating point issues with esp32c3 Missing compiler and link flags Probably since 5.0 --------- Co-authored-by: mikee47 <[email protected]>
SmingHub · Jan 9, 2024 · 22f8c1a · 22f8c1a
1 parent 8edfec9
commit 22f8c1a
Show file tree

Hide file tree

Showing 4 changed files with 28 additions and 2 deletions.
diff --git a/Sming/Arch/Esp32/Components/esp32/sdk/pthread.mk b/Sming/Arch/Esp32/Components/esp32/sdk/pthread.mk
@@ -4,7 +4,10 @@
 SDK_UNDEF_SYMBOLS += \
 	pthread_include_pthread_impl \
 	pthread_include_pthread_cond_impl \
-	pthread_include_pthread_local_storage_impl
+	pthread_include_pthread_cond_var_impl \
+	pthread_include_pthread_local_storage_impl \
+	pthread_include_pthread_rwlock_impl \
+	pthread_include_pthread_semaphore_impl
 
 ifdef CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP
 SDK_WRAP_SYMBOLS += vPortCleanUpTCB

diff --git a/Sming/Arch/Esp32/Components/esp32/sdk/soc.mk b/Sming/Arch/Esp32/Components/esp32/sdk/soc.mk
@@ -0,0 +1,8 @@
+#
+# soc
+#
+
+ifeq (esp32,$(SMING_SOC))
+	SDK_UNDEF_SYMBOLS += \
+		esp_dport_access_reg_read
+endif
diff --git a/Sming/Arch/Esp32/app.mk b/Sming/Arch/Esp32/app.mk
@@ -9,6 +9,12 @@ LDFLAGS	+= \
 	-nostdlib \
 	-Wl,-static
 
+ifdef IDF_TARGET_ARCH_RISCV
+	LDFLAGS += \
+		-nostartfiles \
+		-march=$(ESP32_RISCV_ARCH) \
+		--specs=nosys.specs
+endif
 
 .PHONY: application
 application: $(TARGET_BIN)

diff --git a/Sming/Arch/Esp32/build.mk b/Sming/Arch/Esp32/build.mk
@@ -41,6 +41,12 @@ ESP32_COMPILER_PREFIX := xtensa-$(ESP_VARIANT)-elf
 else
 ESP32_COMPILER_PREFIX := riscv32-esp-elf
 IDF_TARGET_ARCH_RISCV := 1
+# This is important as no hardware FPU is available on these SOCs
+ifeq ($(IDF_VERSION),v5.2)
+ESP32_RISCV_ARCH := rv32imc_zicsr_zifencei
+else
+ESP32_RISCV_ARCH := rv32imc
+endif
 endif
 
 # $1 => Tool sub-path/name
@@ -153,7 +159,10 @@ export PROJECT_VER
 # Flags which control code generation and dependency generation, both for C and C++
 CPPFLAGS += -Wno-frame-address
 
-ifndef IDF_TARGET_ARCH_RISCV
+ifdef IDF_TARGET_ARCH_RISCV
+CPPFLAGS += \
+	-march=$(ESP32_RISCV_ARCH)
+else
 CPPFLAGS += \
 	-mlongcalls \
 	-mtext-section-literals