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Linux ARM64 bus error fix proposal. #25

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64 changes: 64 additions & 0 deletions src/asm/trampoline-aarch64.S
Original file line number Diff line number Diff line change
Expand Up @@ -76,3 +76,67 @@ ret_ctx:
.globl MANGLE(mmk_trampoline_end)
MANGLE(mmk_trampoline_end):
nop

.align 8
.globl MANGLE(mmk_clear_cache)
MANGLE(mmk_clear_cache):
cache_start:
sub sp, sp, #80
str x0, [sp, 8]
str x1, [sp]
ldr x0, [sp, 8]
str x0, [sp, 56]
ldr x1, [sp, 56]
ldr x0, [sp]
add x0, x1, x0
str x0, [sp, 48]
mrs x0, ctr_el0 // Fetching cache type for Data/Instruction Cache
str x0, [sp, 40]
ldr x0, [sp, 40]
lsr x1, x0, 16
mov w0, w1
and w0, w0, 15
mov w1, 4
lsl w0, w1, w0
sxtw x0, w0
str x0, [sp, 32]
ldr x0, [sp, 56]
b cache_cvau
cvau_loop:
ldr x0, [sp, 72]
dc cvau, x0 // Invalidate Data cache line with 64 bits register
ldr x1, [sp, 72]
ldr x0, [sp, 32]
add x0, x1, x0
str x0, [sp, 72]
cache_cvau:
ldr x1, [sp, 72]
ldr x0, [sp, 48]
cmp x1, x0
bcc cvau_loop
dsb ish
ldr x0, [sp, 40]
and w0, w0, 15
mov w1, 4
lsl w0, w1, w0
sxtw x0, w0
str x0, [sp, 24]
ldr x0, [sp, 56]
str x0, [sp, 64]
b cache_isb
cache_ivau:
ldr x0, [sp, 64]
ic ivau, x0 // Invalidate Instruction cache line withh 64 bits register
ldr x1, [sp, 64]
ldr x0, [sp, 24]
add x0, x1, x0
str x0, [sp, 64]
cache_isb:
ldr x1, [sp, 64]
ldr x0, [sp, 48]
cmp x1, x0
bcc cache_ivau
isb sy
mov w0, 0
add sp, sp, 80
ret
6 changes: 6 additions & 0 deletions src/trampoline.c
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,10 @@
extern void mmk_trampoline();
extern void mmk_trampoline_end();

#if defined(__aarch64__)
extern void mmk_clear_cache(void *, size_t);
#endif

#if defined HAVE_MMAP
# include <unistd.h>
# include <sys/mman.h>
Expand Down Expand Up @@ -87,6 +91,8 @@ plt_fn *create_trampoline(void *ctx, plt_fn *routine)
mmk_assert(!mmk_mprotect(map, PAGE_SIZE, PROT_READ | PROT_EXEC));
# if defined __APPLE__
sys_icache_invalidate(map, PAGE_SIZE);
# elif defined(__aarch64__)
mmk_clear_cache(map, PAGE_SIZE);
# elif defined __clang__ // Check for Clang first, it may set __GNUC__ too.
__clear_cache(map, map + PAGE_SIZE);
# elif defined __GNUC__
Expand Down