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32 changes: 22 additions & 10 deletions source/locale/gettext/SpinalHDL/Structuring/blackbox.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-02-26 14:01+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -144,38 +144,50 @@ msgstr ""
msgid "For example:"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:167
#: ../../SpinalHDL/Structuring/blackbox.rst:166
msgid "By default the ports of the blackbox are considered clock-less, meaning no clock crossing checks will be made on their usage. You can specify ports clock domain by using the ClockDomainTag :"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:183
msgid "You can also apply the tag to the whole bundle with :"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:193
msgid "You can also apply the current clock domain to all the ports using (SpinalHDL 1.10.2):"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:204
msgid "io prefix"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:169
#: ../../SpinalHDL/Structuring/blackbox.rst:206
msgid "In order to avoid the prefix \"io\\_\" on each of the IOs of the blackbox, you can use the function ``noIoPrefix()`` as shown below :"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:202
#: ../../SpinalHDL/Structuring/blackbox.rst:239
msgid "Rename all io of a blackbox"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:204
#: ../../SpinalHDL/Structuring/blackbox.rst:241
msgid "IOs of a ``BlackBox`` or ``Component`` can be renamed at compile-time using the ``addPrePopTask`` function. This function takes a no-argument function to be applied during compilation, and is useful for adding renaming passes, as shown in the following example:"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:251
#: ../../SpinalHDL/Structuring/blackbox.rst:288
msgid "Add RTL source"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:253
#: ../../SpinalHDL/Structuring/blackbox.rst:290
msgid "With the function ``addRTLPath()`` you can associate your RTL sources with the blackbox. After the generation of your SpinalHDL code you can call the function ``mergeRTLSource`` to merge all of the sources together."
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:291
#: ../../SpinalHDL/Structuring/blackbox.rst:328
msgid "VHDL - No numeric type"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:293
#: ../../SpinalHDL/Structuring/blackbox.rst:330
msgid "If you want to use only ``std_logic_vector`` in your blackbox component, you can add the tag ``noNumericType`` to the blackbox."
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:312
#: ../../SpinalHDL/Structuring/blackbox.rst:349
msgid "The code above will generate the following VHDL:"
msgstr ""
148 changes: 83 additions & 65 deletions source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po
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@@ -1,23 +1,26 @@

msgid ""
msgstr ""
"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
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"charset=UTF-8\n"
"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
">Language-Team:LANGUAGE <[email protected]>MIME-Version:1.0Content-Type:text/plain; "
"charset=UTF-8\n"
"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-"
"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-"
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"<EMAIL@ADDRESS>Language-Team:LANGUAGE <[email protected]>MIME-Version:1.0Content-"
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"POT-Creation-Date: 2024-02-26 14:01+0000\n"
"PO-Revision-Date: 2023-12-19 09:38+0000\n"
"Last-Translator: Readon <[email protected]>\n"
"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
"spinaldoc-rtd/spinalhdlstructuringblackbox/zh_Hans/>\n"
"Language: zh_CN\n"
"Content-Type: text/plain; charset=UTF-8\n"
"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects"
"/spinaldoc-rtd/spinalhdlstructuringblackbox/zh_Hans/>\n"
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#: ../../SpinalHDL/Structuring/blackbox.rst:4
msgid "Instantiate VHDL and Verilog IP"
Expand All @@ -29,11 +32,10 @@ msgstr "描述"

#: ../../SpinalHDL/Structuring/blackbox.rst:9
msgid ""
"A blackbox allows the user to integrate an existing VHDL/Verilog component "
"into the design by just specifying its interfaces. It's up to the simulator "
"or synthesizer to do the elaboration correctly."
msgstr "黑盒允许用户通过指定其接口将现有的 VHDL/Verilog "
"组件集成到设计中。正确地进行实力细化取决于仿真器或综合器。"
"A blackbox allows the user to integrate an existing VHDL/Verilog "
"component into the design by just specifying its interfaces. It's up to "
"the simulator or synthesizer to do the elaboration correctly."
msgstr "黑盒允许用户通过指定其接口将现有的 VHDL/Verilog 组件集成到设计中。正确地进行实力细化取决于仿真器或综合器。"

#: ../../SpinalHDL/Structuring/blackbox.rst:13
msgid "Defining an blackbox"
Expand All @@ -45,13 +47,14 @@ msgstr "下面示例显示了定义黑盒的方法："

#: ../../SpinalHDL/Structuring/blackbox.rst:46
msgid ""
"In VHDL, signals of type ``Bool`` will be translated into ``std_logic`` and "
"``Bits`` into ``std_logic_vector``. If you want to get ``std_ulogic``, you "
"have to use a ``BlackBoxULogic`` instead of ``BlackBox``."
"In VHDL, signals of type ``Bool`` will be translated into ``std_logic`` "
"and ``Bits`` into ``std_logic_vector``. If you want to get "
"``std_ulogic``, you have to use a ``BlackBoxULogic`` instead of "
"``BlackBox``."
msgstr ""
"在 VHDL 中， ``Bool`` 类型的信号将被转换为 ``std_logic`` ， ``Bits`` "
"将被转换为 ``std_logic_vector``。如果你想获得 ``std_ulogic``，你必须使用 "
"``BlackBoxULogic`` 而不是 ``BlackBox``。"
"在 VHDL 中， ``Bool`` 类型的信号将被转换为 ``std_logic`` ， ``Bits`` 将被转换为 "
"``std_logic_vector``。如果你想获得 ``std_ulogic``，你必须使用 ``BlackBoxULogic`` 而不是 "
"``BlackBox``。"

#: ../../SpinalHDL/Structuring/blackbox.rst:47
msgid "In Verilog, ``BlackBoxUlogic`` does not change the generated verilog."
Expand All @@ -70,8 +73,7 @@ msgid "Instantiating a blackbox"
msgstr "实例化黑盒"

#: ../../SpinalHDL/Structuring/blackbox.rst:77
msgid ""
"Instantiating a ``BlackBox`` is just like instantiating a ``Component``:"
msgid "Instantiating a ``BlackBox`` is just like instantiating a ``Component``:"
msgstr "实例化一个 ``BlackBox`` 就像实例化一个 ``Component`` 一样："

#: ../../SpinalHDL/Structuring/blackbox.rst:115
Expand All @@ -80,14 +82,15 @@ msgstr "时钟和复位信号的映射"

#: ../../SpinalHDL/Structuring/blackbox.rst:117
msgid ""
"In your blackbox definition you have to explicitly define clock and reset "
"wires. To map signals of a ``ClockDomain`` to corresponding inputs of the "
"blackbox you can use the ``mapClockDomain`` or ``mapCurrentClockDomain`` "
"function. ``mapClockDomain`` has the following parameters:"
"In your blackbox definition you have to explicitly define clock and reset"
" wires. To map signals of a ``ClockDomain`` to corresponding inputs of "
"the blackbox you can use the ``mapClockDomain`` or "
"``mapCurrentClockDomain`` function. ``mapClockDomain`` has the following "
"parameters:"
msgstr ""
"在黑盒定义中，您必须明确定义时钟和复位线。要将 ``ClockDomain`` "
"的信号映射到黑盒的相应输入，您可以使用 ``mapClockDomain`` 或 "
"``mapCurrentClockDomain`` 函数。 ``mapClockDomain`` 具有以下参数："
"在黑盒定义中，您必须明确定义时钟和复位线。要将 ``ClockDomain`` 的信号映射到黑盒的相应输入，您可以使用 "
"``mapClockDomain`` 或 ``mapCurrentClockDomain`` 函数。 ``mapClockDomain`` "
"具有以下参数："

#: ../../SpinalHDL/Structuring/blackbox.rst:123
msgid "name"
Expand Down Expand Up @@ -161,63 +164,78 @@ msgstr "黑盒输入应连接到时钟域的使能信号"
msgid ""
"``mapCurrentClockDomain`` has almost the same parameters as "
"``mapClockDomain`` but without the clockDomain."
msgstr "``mapCurrentClockDomain`` 具有与 ``mapClockDomain`` "
"几乎相同的参数，但没有时钟域。"
msgstr "``mapCurrentClockDomain`` 具有与 ``mapClockDomain`` 几乎相同的参数，但没有时钟域。"

#: ../../SpinalHDL/Structuring/blackbox.rst:147
msgid "For example:"
msgstr "例如："

#: ../../SpinalHDL/Structuring/blackbox.rst:167
#: ../../SpinalHDL/Structuring/blackbox.rst:166
msgid ""
"By default the ports of the blackbox are considered clock-less, meaning "
"no clock crossing checks will be made on their usage. You can specify "
"ports clock domain by using the ClockDomainTag :"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:183
msgid "You can also apply the tag to the whole bundle with :"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:193
msgid ""
"You can also apply the current clock domain to all the ports using "
"(SpinalHDL 1.10.2):"
msgstr ""

#: ../../SpinalHDL/Structuring/blackbox.rst:204
msgid "io prefix"
msgstr "io前缀"

#: ../../SpinalHDL/Structuring/blackbox.rst:169
#: ../../SpinalHDL/Structuring/blackbox.rst:206
msgid ""
"In order to avoid the prefix \"io\\_\" on each of the IOs of the blackbox, "
"you can use the function ``noIoPrefix()`` as shown below :"
msgstr "为了避免黑盒的每个 IO 上都有前缀 \"io\\_\" ，可以使用函数 ``noIoPrefix()`` "
"，如下所示："
"In order to avoid the prefix \"io\\_\" on each of the IOs of the "
"blackbox, you can use the function ``noIoPrefix()`` as shown below :"
msgstr "为了避免黑盒的每个 IO 上都有前缀 \"io\\_\" ，可以使用函数 ``noIoPrefix()`` ，如下所示："

#: ../../SpinalHDL/Structuring/blackbox.rst:202
#: ../../SpinalHDL/Structuring/blackbox.rst:239
msgid "Rename all io of a blackbox"
msgstr "重命名黑盒中的所有io"

#: ../../SpinalHDL/Structuring/blackbox.rst:204
#: ../../SpinalHDL/Structuring/blackbox.rst:241
msgid ""
"IOs of a ``BlackBox`` or ``Component`` can be renamed at compile-time using "
"the ``addPrePopTask`` function. This function takes a no-argument function "
"to be applied during compilation, and is useful for adding renaming passes, "
"as shown in the following example:"
"IOs of a ``BlackBox`` or ``Component`` can be renamed at compile-time "
"using the ``addPrePopTask`` function. This function takes a no-argument "
"function to be applied during compilation, and is useful for adding "
"renaming passes, as shown in the following example:"
msgstr ""
"``BlackBox`` 或 ``Component`` 的 IO 可以在编译时使用 ``addPrePopTask`` 函数重"
"命名。此函数在编译期间调用一个无参数函数，对于添加重命名通道非常有用，如下所"
"示："
"``BlackBox`` 或 ``Component`` 的 IO 可以在编译时使用 ``addPrePopTask`` "
"函数重命名。此函数在编译期间调用一个无参数函数，对于添加重命名通道非常有用，如下所示："

#: ../../SpinalHDL/Structuring/blackbox.rst:251
#: ../../SpinalHDL/Structuring/blackbox.rst:288
msgid "Add RTL source"
msgstr "添加 RTL 源"

#: ../../SpinalHDL/Structuring/blackbox.rst:253
#: ../../SpinalHDL/Structuring/blackbox.rst:290
msgid ""
"With the function ``addRTLPath()`` you can associate your RTL sources with "
"the blackbox. After the generation of your SpinalHDL code you can call the "
"function ``mergeRTLSource`` to merge all of the sources together."
"With the function ``addRTLPath()`` you can associate your RTL sources "
"with the blackbox. After the generation of your SpinalHDL code you can "
"call the function ``mergeRTLSource`` to merge all of the sources "
"together."
msgstr ""
"使用函数 ``addRTLPath()`` ，您可以将 RTL 源与黑盒关联起来。生成 SpinalHDL "
"代码后，您可以调用函数 ``mergeRTLSource`` 将所有源合并在一起。"
"使用函数 ``addRTLPath()`` ，您可以将 RTL 源与黑盒关联起来。生成 SpinalHDL 代码后，您可以调用函数 "
"``mergeRTLSource`` 将所有源合并在一起。"

#: ../../SpinalHDL/Structuring/blackbox.rst:291
#: ../../SpinalHDL/Structuring/blackbox.rst:328
msgid "VHDL - No numeric type"
msgstr "VHDL - 无数值类型"

#: ../../SpinalHDL/Structuring/blackbox.rst:293
#: ../../SpinalHDL/Structuring/blackbox.rst:330
msgid ""
"If you want to use only ``std_logic_vector`` in your blackbox component, you"
" can add the tag ``noNumericType`` to the blackbox."
msgstr "如果您只想在黑盒组件中使用 ``std_logic_vector`` ，则可以将标签 "
"``noNumericType`` 添加到黑盒中。"
"If you want to use only ``std_logic_vector`` in your blackbox component, "
"you can add the tag ``noNumericType`` to the blackbox."
msgstr "如果您只想在黑盒组件中使用 ``std_logic_vector`` ，则可以将标签 ``noNumericType`` 添加到黑盒中。"

#: ../../SpinalHDL/Structuring/blackbox.rst:312
#: ../../SpinalHDL/Structuring/blackbox.rst:349
msgid "The code above will generate the following VHDL:"
msgstr "上面的代码将生成以下 VHDL："

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