try to fix problems related to new anasymod version

dragonphy/anasymod.py

@@ -4,7 +4,7 @@
 DEF_DT_WIDTH = 25
 
 class AnasymodProjectConfig:
-    def __init__(self, fpga_sim_ctrl='UART_ZYNQ'):
+    def __init__(self, fpga_sim_ctrl='UART_ZYNQ', custom_zynq_firmware=True):
         # validate input
         assert fpga_sim_ctrl in {'UART_ZYNQ', 'VIVADO_VIO'}, 'Invalid setting.'
 
@@ -23,7 +23,8 @@ def __init__(self, fpga_sim_ctrl='UART_ZYNQ'):
             },
             'FPGA_TARGET': {
                 'fpga': {
-                    'fpga_sim_ctrl': fpga_sim_ctrl
+                    'fpga_sim_ctrl': fpga_sim_ctrl,
+                    'custom_zynq_firmware': custom_zynq_firmware
                 }
             }
         }
@@ -56,6 +57,9 @@ def add_plugin(self, arg):
     def set_emu_clk_freq(self, value):
         self.config['PROJECT']['emu_clk_freq'] = value
 
+    def set_custom_zynq_firmware(self, value):
+        self.config['FPGA_TARGET']['fpga']['custom_zynq_firmware'] = value
+
     def write_to_file(self, fname):
         with open(fname, 'w') as f:
             yaml.dump(self.config, f, sort_keys=False)

tests/fpga_system_tests/emu/test_emu.py

@@ -108,19 +108,7 @@ def test_3():
     ana.set_target(target_name='fpga')
     ana.build()
 
-def test_4():
-    # build ELF
-    ana = Analysis(input=str(THIS_DIR))
-    ana.set_target(target_name='fpga')
-    ana.build_firmware()
-
-def test_5():
-    # download program
-    ana = Analysis(input=str(THIS_DIR))
-    ana.set_target(target_name='fpga')
-    ana.program_firmware()
-
-def test_6(prbs_test_dur, jitter_rms, noise_rms, chan_tau, chan_delay):
+def test_4(prbs_test_dur, jitter_rms, noise_rms, chan_tau, chan_delay):
     # read ffe_length
     SYSTEM = yaml.load(open(get_file('config/system.yml'), 'r'), Loader=yaml.FullLoader)
     ffe_length = SYSTEM['generic']['ffe']['parameters']['length']

tests/fpga_system_tests/emu_macro/test_emu_macro.py

@@ -111,19 +111,7 @@ def test_3():
     ana.set_target(target_name='fpga')
     ana.build()
 
-def test_4():
-    # build ELF
-    ana = Analysis(input=str(THIS_DIR))
-    ana.set_target(target_name='fpga')
-    ana.build_firmware()
-
-def test_5():
-    # download program
-    ana = Analysis(input=str(THIS_DIR))
-    ana.set_target(target_name='fpga')
-    ana.program_firmware()
-
-def test_6(prbs_test_dur, jitter_rms, noise_rms, chan_tau, chan_delay):
+def test_4(prbs_test_dur, jitter_rms, noise_rms, chan_tau, chan_delay):
     # read ffe_length
     SYSTEM = yaml.load(open(get_file('config/system.yml'), 'r'), Loader=yaml.FullLoader)
     ffe_length = SYSTEM['generic']['ffe']['parameters']['length']