Cpuif properties

docs/index.rst

@@ -98,6 +98,7 @@ Links
     :caption: Extended Properties
 
     udps/intro
+    udps/cpuif
     udps/read_buffering
     udps/write_buffering
     udps/extended_swacc

docs/udps/cpuif.rst

@@ -0,0 +1,51 @@
+.. _cpuif:
+
+CPU Interface
+=============
+
+Properties
+----------
+The CPU interface for the registers can be specified with the following properties:
+
+.. literalinclude:: ../../hdl-src/regblock_udps.rdl
+    :lines: 40-48
+
+This UDP definition, along with others supported by PeakRDL-regblock can be
+enabled by compiling the following file along with your design:
+:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
+
+.. describe:: cpuif
+
+    *   Assigned value is a string.
+    *   Specifies the CPU interface type to access the registers.
+
+.. describe:: addrwidth
+
+    *   Assigned value is a longint unsigned.
+    *   Specifies the width of the CPU interface's address bus.
+
+Example
+-------
+
+In this example, an axi4-lite CPU interface is specified with an address bus
+width of 8.
+
+.. code-block:: systemrdl
+    :emphasize-lines: 4
+
+    addrmap top {
+        cpuif = "axi4-lite";
+        addrwidth = 8;
+
+        reg {
+            field {} rst;
+            field {} en;
+            field {} start;
+            field {} stop;
+        } control;
+
+        reg {
+            field {} running;
+            field {} done;
+        } status;
+    };

docs/udps/intro.rst

@@ -19,6 +19,20 @@ To enable these UDPs, compile this RDL file prior to the rest of your design:
         - Type
         - Description
 
+    *   - cpuif
+        - addrmap
+        - string
+        - Specifies the CPU interface type.
+
+          See: :ref:`cpuif`.
+
+    *   - addrwidth
+        - addrmap
+        - longint unsigned
+        - Specifies the address with of the CPU interface.
+
+          See: :ref:`cpuif`.
+
     *   - buffer_reads
         - reg
         - boolean

hdl-src/regblock_udps.rdl

@@ -36,3 +36,13 @@ property wr_swacc {
     component = field;
     type = boolean;
 };
+
+property cpuif {
+    component = addrmap;
+    type = string;
+};
+
+property addrwidth {
+    component = addrmap;
+    type = longint unsigned;
+};

src/peakrdl_regblock/__peakrdl__.py

@@ -86,7 +86,6 @@ def add_exporter_arguments(self, arg_group: 'argparse.ArgumentParser') -> None:
         arg_group.add_argument(
             "--cpuif",
             choices=cpuifs.keys(),
-            default="apb3",
             help="Select the CPU interface protocol to use [apb3]"
         )
 
@@ -202,12 +201,25 @@ def do_export(self, top_node: 'AddrmapNode', options: 'argparse.Namespace') -> N
         else:
             raise RuntimeError
 
+        # Get cpuif. Favor command-line over SystemRDL, defaults to apb3.
+        if options.cpuif is not None:
+            cpuif = cpuifs[options.cpuif]
+        elif top_node.get_property('cpuif') is not None:
+            cpuif_name = top_node.get_property('cpuif')
+            if cpuif_name not in cpuifs:
+                raise RuntimeError(f"error: unknown cpuif: {cpuif_name} (choose from: {' '.join(cpuifs.keys())})")
+            cpuif = cpuifs[cpuif_name]
+        else:
+            cpuif = cpuifs['apb3']
+
+        # Get cpuif addr_width. Favor command-line over SystemRDL.
+        addr_width = options.addr_width or top_node.get_property('addrwidth')
 
         x = RegblockExporter()
         x.export(
             top_node,
             options.output,
-            cpuif_cls=cpuifs[options.cpuif],
+            cpuif_cls=cpuif,
             module_name=options.module_name,
             package_name=options.package_name,
             reuse_hwif_typedefs=(options.type_style == "lexical"),
@@ -218,7 +230,7 @@ def do_export(self, top_node: 'AddrmapNode', options: 'argparse.Namespace') -> N
             retime_external_mem=retime_external_mem,
             retime_external_addrmap=retime_external_addrmap,
             generate_hwif_report=options.hwif_report,
-            address_width=options.addr_width,
+            address_width=addr_width,
             default_reset_activelow=default_reset_activelow,
             default_reset_async=default_reset_async,
         )

src/peakrdl_regblock/udps/__init__.py

@@ -1,6 +1,7 @@
 from .rw_buffering import BufferWrites, WBufferTrigger
 from .rw_buffering import BufferReads, RBufferTrigger
 from .extended_swacc import ReadSwacc, WriteSwacc
+from .cpuif import CpuIf, AddrWidth
 
 ALL_UDPS = [
     BufferWrites,
@@ -9,4 +10,6 @@
     RBufferTrigger,
     ReadSwacc,
     WriteSwacc,
+    CpuIf,
+    AddrWidth,
 ]

src/peakrdl_regblock/udps/cpuif.py

@@ -0,0 +1,24 @@
+from typing import TYPE_CHECKING, Any
+
+from systemrdl.udp import UDPDefinition
+from systemrdl.component import Addrmap
+
+if TYPE_CHECKING:
+    from systemrdl.node import Node
+
+class CpuIf(UDPDefinition):
+    name = "cpuif"
+    valid_components = {Addrmap}
+    valid_type = str
+
+    def get_unassigned_default(self, node: 'Node') -> Any:
+        return None
+
+
+class AddrWidth(UDPDefinition):
+    name = "addrwidth"
+    valid_components = {Addrmap}
+    valid_type = int
+
+    def get_unassigned_default(self, node: 'Node') -> Any:
+        return None