This Repository is a step wise design of RISC-V Single cycle processor .
The Design of RISCV_SINGLE_CYCLE Processor is divided into 4 stages.
See the file Phases_RISCV_Single-Cycle_Processor.pdf to learn more about each phases {or each steps in design}. Phases_RISC-V_SINGLE_CYCLE_PROCESSOR.pdf
For more detailed study of each components in each phase refer TB --> Computer organization and design- RISC-V edition by David A patterson {Chapter = The Processor} {Prerequist knowledge of RISC-V Processor Design is required to undertand this repository}
The below riscv_report.pdf contains all the necessary codes and the required explanation for each phase and at last for whole RISCV-Module . The report also Contains Simualtion Results and explanation , Code Coverage Report, Synthesis Report {power,area and timing reports} and Physical Design for final riscv module. riscv_report.pdf
Note the Tools Used :
Simulation and Code Coverage: Cadence Incisive Simulator;
Synthesis : Cadence Genus;
Physical Design : Cadence Innovus
Also Use the below slides riscv_slides.pdf created for above report for presentation . riscv_slides.pdf
Note that there are many repositories for riscv_single_cycle but this repository contains detail step by step {phases} and each component design in that phase for RISC-V Datapath and the Control Signal generation for RISC-V Control Unit