asap7/ethmac - reduce the clock period to create more optimization ch…

…allenge | Metric | Old | New | Type | | ------ | --- | --- | ---- | | detailedroute__route__wirelength | 580232 | 560374 | Tighten | | finish__timing__setup__ws | -9.61 | -160.71 | Failing | | finish__timing__wns_percent_delay | -10.0 | -44.96 | Failing | Signed-off-by: Matt Liberty <[email protected]>
The-OpenROAD-Project · Aug 22, 2024 · 345e5b1 · 345e5b1
1 parent c6ea30d
commit 345e5b1
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Showing 3 changed files with 217 additions and 216 deletions.
diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc
@@ -1,5 +1,5 @@
 set top_clk_name wb_clk_i
-set clk_period 1500
+set clk_period 1000
 set clk_io_pct 0.2
 set clk_port [get_ports $top_clk_name]
 create_clock -name $top_clk_name -period $clk_period $clk_port
@@ -9,15 +9,15 @@ set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outp
 
 set tx_clk_name mtx_clk_pad_i
 set tx_clk_port [get_ports $tx_clk_name]
-set tx_clk_period 500
+set tx_clk_period 300
 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
 set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
 set_input_delay  [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs 
 set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
 
 set rx_clk_name mrx_clk_pad_i
 set rx_clk_port [get_ports $rx_clk_name]
-set rx_clk_period 500
+set rx_clk_period 300
 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
 set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
 set_input_delay  [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs