Complete support for swapping to uninstantiated modules

src/OpenRoad.cc

@@ -548,6 +548,7 @@ void OpenRoad::readVerilog(const char* filename)
   if (verilog_reader_ == nullptr) {
     verilog_reader_ = new sta::VerilogReader(verilog_network_);
   }
+  setDbNetworkLinkFunc(this, verilog_reader_);
   verilog_reader_->read(filename);
 }
 

src/dbSta/include/db_sta/dbReadVerilog.hh

@@ -61,6 +61,7 @@ using sta::Cell;
 using sta::ConcreteCell;
 using sta::ConcreteNetwork;
 using sta::dbNetwork;
+using sta::VerilogReader;
 
 // Hierarchical network for read_verilog.
 // Verilog cells and module networks are built here.
@@ -81,6 +82,9 @@ dbVerilogNetwork* makeDbVerilogNetwork();
 
 void initDbVerilogNetwork(OpenRoad* openroad);
 
+void setDbNetworkLinkFunc(ord::OpenRoad* openroad,
+                          VerilogReader* verilog_reader);
+
 void deleteDbVerilogNetwork(dbVerilogNetwork* verilog_network);
 
 // Read a hierarchical Verilog netlist into a OpenSTA concrete network

src/dbSta/src/dbReadVerilog.cc

@@ -99,6 +99,7 @@ using sta::PinSeq;
 using sta::Port;
 using sta::PortDirection;
 using sta::Term;
+using sta::VerilogReader;
 using utl::Logger;
 
 dbVerilogNetwork::dbVerilogNetwork()
@@ -124,6 +125,22 @@ void initDbVerilogNetwork(ord::OpenRoad* openroad)
   openroad->getVerilogNetwork()->init(sta->getDbNetwork());
 }
 
+void setDbNetworkLinkFunc(ord::OpenRoad* openroad,
+                          VerilogReader* verilog_reader)
+{
+  if (verilog_reader) {
+    openroad->getVerilogNetwork()->setLinkFunc(
+        [=](const char* top_cell_name, bool make_black_boxes) -> Instance* {
+          return verilog_reader->linkNetwork(
+              top_cell_name,
+              make_black_boxes,
+              // don't delete modules after link so we can swap to
+              // uninstantiated modules if needed
+              false);
+        });
+  }
+}
+
 void deleteDbVerilogNetwork(dbVerilogNetwork* verilog_network)
 {
   delete verilog_network;
@@ -879,7 +896,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module)
       debugPrint(logger_,
                  utl::ODB,
                  "dbReadVerilog",
-                 1,
+                 2,
                  "connected iterm {} to mod net {}",
                  iterm->getName(),
                  db_mod_net->getName());
@@ -888,7 +905,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module)
       debugPrint(logger_,
                  utl::ODB,
                  "dbReadVerilog",
-                 1,
+                 2,
                  "connected bterm {} to mod net {}",
                  bterm->getName(),
                  db_mod_net->getName());
@@ -897,7 +914,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module)
       debugPrint(logger_,
                  utl::ODB,
                  "dbReadVerilog",
-                 1,
+                 2,
                  "connected mod_bterm {} to mod net {}",
                  mod_bterm->getName(),
                  db_mod_net->getName());
@@ -906,7 +923,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module)
       debugPrint(logger_,
                  utl::ODB,
                  "dbReadVerilog",
-                 1,
+                 2,
                  "connected mod_iterm {} to mod net {}",
                  mod_iterm->getName(),
                  db_mod_net->getName());

src/dbSta/test/readdb_hier.ok

@@ -15,27 +15,13 @@
 [DEBUG ODB-dbReadVerilog] Created module iterm clk for bterm clk
 [DEBUG ODB-dbReadVerilog] Created module iterm out for bterm out
 [DEBUG ODB-dbReadVerilog] created mod_net in in module top
-[DEBUG ODB-dbReadVerilog] connected mod_iterm in to mod net in
 [DEBUG ODB-dbReadVerilog] created mod_net in in module block1
-[DEBUG ODB-dbReadVerilog] connected iterm b1/u1/A to mod net in
 [DEBUG ODB-dbReadVerilog] created mod_net clk1 in module top
-[DEBUG ODB-dbReadVerilog] connected mod_iterm clk to mod net clk1
 [DEBUG ODB-dbReadVerilog] created mod_net clk in module block1
-[DEBUG ODB-dbReadVerilog] connected iterm b1/r1/CP to mod net clk
 [DEBUG ODB-dbReadVerilog] created mod_net b1out in module top
-[DEBUG ODB-dbReadVerilog] connected mod_iterm out to mod net b1out
-[DEBUG ODB-dbReadVerilog] connected mod_iterm in to mod net b1out
 [DEBUG ODB-dbReadVerilog] created mod_net out in module block1
-[DEBUG ODB-dbReadVerilog] connected iterm b1/u2/Z to mod net out
-[DEBUG ODB-dbReadVerilog] connected mod_iterm out to mod net b1out
-[DEBUG ODB-dbReadVerilog] connected mod_iterm in to mod net b1out
 [DEBUG ODB-dbReadVerilog] created mod_net in in module block1_b2
-[DEBUG ODB-dbReadVerilog] connected iterm b2/u1/A to mod net in
 [DEBUG ODB-dbReadVerilog] created mod_net clk2 in module top
-[DEBUG ODB-dbReadVerilog] connected mod_iterm clk to mod net clk2
 [DEBUG ODB-dbReadVerilog] created mod_net clk in module block1_b2
-[DEBUG ODB-dbReadVerilog] connected iterm b2/r1/CP to mod net clk
 [DEBUG ODB-dbReadVerilog] created mod_net out in module top
-[DEBUG ODB-dbReadVerilog] connected mod_iterm out to mod net out
 [DEBUG ODB-dbReadVerilog] created mod_net out in module block1_b2
-[DEBUG ODB-dbReadVerilog] connected iterm b2/u2/Z to mod net out

src/odb/src/db/dbBlock.h

@@ -291,7 +291,6 @@ class _dbBlock : public _dbObject
   dbBlockSearch* _searchDb;
 
   std::map<std::string, int> _module_name_id_map;
-  std::map<std::string, int> _inst_name_id_map;
 
   unsigned char _num_ext_dbs;
 

src/odb/src/db/dbModule.cpp

@@ -513,6 +513,7 @@ std::vector<dbInst*> dbModule::getLeafInsts()
 dbModBTerm* dbModule::findModBTerm(const char* name)
 {
   std::string modbterm_name(name);
+  // TODO: use proper hierarchy limiter from _dbBlock->_hier_delimiter
   size_t last_idx = modbterm_name.find_last_of('/');
   if (last_idx != std::string::npos) {
     modbterm_name = modbterm_name.substr(last_idx + 1);
@@ -595,6 +596,9 @@ void dbModule::copy(dbModule* old_module,
   copyModuleBoundaryIO(old_module, new_module, new_mod_inst);
 }
 
+// A bus with N members have N+1 modbterms.  The first one is the "bus port"
+// sentinel.   The sentinel has reference to the member size, direction and
+// list of member modbterms.
 void dbModule::copyModulePorts(dbModule* old_module,
                                dbModule* new_module,
                                modBTMap& mod_bt_map)
@@ -672,6 +676,7 @@ void dbModule::copyModulePorts(dbModule* old_module,
                           old_port->getName(),
                           ix);
           }
+          // TODO: use proper bus array delimiter instead of '[' and ']'
           std::string bus_bit_name = std::string(old_port->getName())
                                      + std::string("[") + std::to_string(ix)
                                      + std::string("]");
@@ -727,6 +732,7 @@ void dbModule::copyModuleInsts(dbModule* old_module,
     dbInst* old_inst = *inst_iter;
     // Change unique instance name from old_inst/leaf to new_inst/leaf
     std::string old_inst_name = old_inst->getName();
+    // TODO: use proper hierarchy limiter from _dbBlock->_hier_delimiter
     size_t first_idx = old_inst_name.find_first_of('/');
     std::string new_inst_name;
     if (first_idx != std::string::npos) {
@@ -778,6 +784,7 @@ void dbModule::copyModuleInsts(dbModule* old_module,
       if (old_net) {
         // Create a local net only if it connects to iterms inside this module
         std::string net_name = old_net->getName();
+        // TODO: use proper hierarchy limiter from _dbBlock->_hier_delimiter
         size_t first_idx = net_name.find_first_of('/');
         std::string new_net_name;
         if (first_idx != std::string::npos) {

src/odb/test/CMakeLists.txt

@@ -39,7 +39,7 @@ or_integration_tests(
     replace_design1
     replace_design2
     replace_design3
-#    replace_design4
+    replace_design4
     rounding
     row_settings
     sky130hd_multi_patterned