feat: update project tt_um_lfsr from JamesTimothyMeech/TT07-LFSR

Commit: bb74cc7defcbdaceb39222a537e7146d36a0b6bd
Workflow: https://github.com/JamesTimothyMeech/TT07-LFSR/actions/runs/9302554188

projects/tt_um_lfsr/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt07 98e94823",
+  "app": "Tiny Tapeout tt07 11b2d371",
   "repo": "https://github.com/JamesTimothyMeech/TT07-LFSR",
-  "commit": "d78758f0f253ae3c11d7910b1c7e46ba9820514f",
-  "workflow_url": "https://github.com/JamesTimothyMeech/TT07-LFSR/actions/runs/9270926569",
+  "commit": "bb74cc7defcbdaceb39222a537e7146d36a0b6bd",
+  "workflow_url": "https://github.com/JamesTimothyMeech/TT07-LFSR/actions/runs/9302554188",
   "sort_id": 1716906380254,
   "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_lfsr/docs/info.md

@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-It is a LFSR.
+It is a linear feedback shift register random number generator connected to a wishbone bus to allow it to fit within the pin constraints of Tiny Tapeout. 
 
 ## How to test
 
-Measure the output bit.
+Please see the cocotb testbench in the test.py in the test directory for the startup procedure for loading a seed and starting the linear feedback shift register output. 
 
 ## External hardware
 
-Something to measure the output bit.
+Use the microcontroller on the development board to apply the correct startup signals to the board.

projects/tt_um_lfsr/info.yaml

@@ -1,7 +1,7 @@
 # Tiny Tapeout project information
 project:
   title:        "LFSR"      # Project title
-  author:       "James Meech"      # Your name
+  author:       "James Meech and Werner Florian"      # Your name
   discord:      "Meechy"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "Linear feedback shift register random number generator"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
@@ -22,34 +22,34 @@ project:
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "Wishbone data inputs"
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
-  ui[4]: ""
-  ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[0]: "Wishbone data input bit 0"
+  ui[1]: "Wishbone data input bit 1"
+  ui[2]: "Wishbone data input bit 2"
+  ui[3]: "Wishbone data input bit 3"
+  ui[4]: "Wishbone data input bit 4"
+  ui[5]: "Wishbone data input bit 5"
+  ui[6]: "Wishbone data input bit 6"
+  ui[7]: "Wishbone data input bit 7"
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
-  uo[3]: ""
-  uo[4]: ""
-  uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[0]: "Output bit to indicate whether or not the wishbone has stalled (o_wb_stall)"
+  uo[1]: "LFSR output bit (o_wb_data)"
+  uo[2]: "Output bit for the wishbone to acknowledge the successful end of writing part of the LFSR seed (o_wb_ack)"
+  uo[3]: "Not used in this design"
+  uo[4]: "Not used in this design"
+  uo[5]: "Not used in this design"
+  uo[6]: "Not used in this design"
+  uo[7]: "Not used in this design"
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
-  uio[5]: ""
-  uio[6]: ""
-  uio[7]: ""
+  uio[0]: "Wishbone input bit to indicate that a valid bus cycle is in progress (i_wb_cyc, hardcoded as an input)"
+  uio[1]: "Wishbone chipselect input bit to indicate a valid seed data transfer cycle (i_wb_stb, hardcoded as an input)"
+  uio[2]: "Wishbone input bit to indicate a read or a write cycle read = 0, write = 1 (i_wb_we, hardcoded as an input)"
+  uio[3]: "Wishbone input address bit zero to select which eight bit byte of the seed to write (i_wb_addr[0])"
+  uio[4]: "Wishbone input address bit one to select which eight bit byte of the seed to write (i_wb_addr[1])"
+  uio[5]: "Wishbone input address bit two to select which eight bit byte of the seed to write (i_wb_addr[2])"
+  uio[6]: "Not used in this design"
+  uio[7]: "Not used in this design"
 
 # Do not change!
 yaml_version: 6

projects/tt_um_lfsr/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_lfsr,wokwi,flow completed,0h1m1s0ms,0h0m43s0ms,38764.180115312294,0.01795472,19382.090057656147,18.39,24.624499999999998,516.74,259,0,0,0,0,0,0,0,0,0,0,-1,-1,5779,1960,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,3267372.0,0.0,13.26,8.75,1.39,1.18,-1,314,482,285,453,0,0,0,130,2,32,2,0,4,1,2,35,82,100,5,1006,225,0,269,348,1848,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_lfsr,wokwi,flow completed,0h1m2s0ms,0h0m44s0ms,38764.180115312294,0.01795472,19382.090057656147,18.39,24.624499999999998,516.96,259,0,0,0,0,0,0,0,0,0,0,-1,-1,5779,1960,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,3267372.0,0.0,13.26,8.75,1.39,1.18,-1,314,482,285,453,0,0,0,130,2,32,2,0,4,1,2,35,82,100,5,1006,225,0,269,348,1848,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_lfsr/tt_um_lfsr.spef

@@ -1,6 +1,6 @@
 *SPEF "ieee 1481-1999"
 *DESIGN "tt_um_lfsr"
-*DATE "14:13:09 Tuesday May 28, 2024"
+*DATE "12:33:24 Thursday May 30, 2024"
 *VENDOR "The OpenROAD Project"
 *PROGRAM "OpenROAD"
 *VERSION "da0053d7b0014ab9c87ea148875ff6c2a0f9b658"