feat: update project tt_um_nurirfansyah_alits02 from nurirfansyah/tt0…

…7-analog-its_ip_alits02

Commit: 849cd71f5889bed5b6662eb2add5b64b37b2bf3e
Workflow: https://github.com/nurirfansyah/tt07-analog-its_ip_alits02/actions/runs/9332725565

projects/tt_um_nurirfansyah_alits02/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "custom_gds action",
   "repo": "https://github.com/nurirfansyah/tt07-analog-its_ip_alits02",
-  "commit": "8436eb79e5e8f8b219fe8190f350a564b1b90755",
-  "workflow_url": "https://github.com/nurirfansyah/tt07-analog-its_ip_alits02/actions/runs/9332662470",
+  "commit": "849cd71f5889bed5b6662eb2add5b64b37b2bf3e",
+  "workflow_url": "https://github.com/nurirfansyah/tt07-analog-its_ip_alits02/actions/runs/9332725565",
   "sort_id": 1717265794550,
   "analog": true
 }

projects/tt_um_nurirfansyah_alits02/docs/info.md

@@ -12,30 +12,26 @@ You can also include images in this folder and reference them in the markdown. E
 This tinytapeout submission consists of:
 1. A VCO based on transmission gates with additional on-chip capacitors to further linearize the response.
 2. A phase detector and VCO to form parts of a PLL.
-3. Basic CMOS Opamp
 
 ## How to test
 
 Pinouts:
 
 Analog pins:
 
-ua[0] - VCO (PLL) output
+ua[0] - VCO #1 output
 
-ua[1] - Opamp input (+) / Phase Detector (PLL) ref
+ua[1] - VCO#1 VCONT- / Phase Detector (PLL) ref
 
-ua[2] - Opamp input (+) / Phase Detector (PLL) input / PLL feedback
+ua[2] - VCO#1 VCONT+ / Phase Detector (PLL) input / PLL feedback
 
-ua[3] - Opamp output
+ua[3] - PLL VCO output
 
-ua[4] - PLL Filter + / VCO#1 control input voltage (-) 
+ua[4] - PLL Filter (n)  
 
-ua[5] - PLL Filter - / VCO#1 control input voltage (+)
+ua[5] - PLL Filter (p)
 
-Digital pins:
-
-o[0] - VCO#1 output
 
 ## External hardware
 
-To test, typical experimental setup to test opamp, pll, or vco, would be required.
+To test, typical experimental setup to test pll, or vco, would be required.

projects/tt_um_nurirfansyah_alits02/info.yaml

@@ -1,9 +1,9 @@
 # Tiny Tapeout project information
 project:
   title:        "Analog Test Circuit ITS 2"      # Project title
-  author:       "Astria Nur Irfansyah"      # Your name
+  author:       "A. N Irfansyah, Raditya Eka, Yohanes Stefanus"      # Your name
   discord:      "irfansyah_99806"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "VCO"      # One line description of what your project does
+  description:  "PLL parts (VCO and phase detector)"      # One line description of what your project does
   language:     "Analog" # other examples include Verilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
@@ -53,12 +53,12 @@ pinout:
   uio[7]: ""
 
   # Analog pins - make sure to also set "analog_pins" above, else the pins won't be connected
-  ua[0]: "in0"
-  ua[1]: "in1"
-  ua[2]: "in2"
-  ua[3]: "out1"
-  ua[4]: "out2"
-  ua[5]: "out3"
+  ua[0]: "vco1_out"
+  ua[1]: "vco1_in-"
+  ua[2]: "vco1_in+"
+  ua[3]: "pllvco_out"
+  ua[4]: "pllfilter_n"
+  ua[5]: "pllfilter_p"
 
 # Do not change!
 yaml_version: 6