Add some tests for the parser

README.md

@@ -1,13 +1,13 @@
 <h1 align="center">HELM <a href="https://github.com/jimouris/helm/blob/main/LICENSE"><img src="https://img.shields.io/badge/license-MIT-blue.svg"></a> </h1>
 
-<h2 align="center">HELM: Homomorphic Evaluation with Lookup table Memoization</h2>
+<h2 align="center">HELM: Navigating Homomorphic Evaluation through Gates and Lookups</h2>
 
 
 ## Overview
 HELM is a framework for evaluating synthesizable HDL designs in the encrypted
 domain that is designed for multi-core CPU evaluation. Users can choose between
 evaluating circuits composed of standard Boolean gates, low-precision LUTs, or
-high-precision arithmetic operations. 
+high-precision arithmetic operations.
 In all cases, both sequential and combinational circuits are supported with the
 exception of arithmetic circuits (which only support combinational logic).
 
@@ -55,7 +55,7 @@ You can also pass the input wire values as:
 ```shell
 cargo run --bin helm --release -- \
     --verilog ./hdl-benchmarks/processed-netlists/2-bit-adder.v \
-    -w a[0] 1 -w a[1] 0 -w b[0] 0 -w b[1] 1 -w cin 0 
+    -w a[0] 1 -w a[1] 0 -w b[0] 0 -w b[1] 1 -w cin 0
 ```
 
 

src/lib.rs

@@ -146,7 +146,7 @@ pub fn get_input_wire_map(
 
 pub fn parse_args() -> ArgMatches {
     Command::new("HELM")
-        .about("HELM: Homomorphic Evaluation with EDA-driven Logic Minimization")
+        .about("HELM: Navigating Homomorphic Evaluation through Gates and Lookups")
         .arg(
             Arg::new("verilog")
                 .long("verilog")

src/verilog_parser.rs

@@ -285,7 +285,10 @@ pub fn read_input_wires(file_name: &str, ptxt_type: &str) -> HashMap<String, Ptx
         let input_wire = record[0].trim().to_string();
         match ptxt_type {
             "bool" => {
-                let init_value = record[1].trim().to_string().parse::<bool>().unwrap();
+                let init_value = match record[1].trim() {
+                    "1" => true,
+                    s => s.parse::<bool>().unwrap_or(false),
+                };
                 input_map.insert(input_wire, PtxtType::Bool(init_value));
             }
             "u8" => {

tests/verilog_parser_test.rs

@@ -1,4 +1,5 @@
 use helm::verilog_parser::{read_input_wires, read_verilog_file};
+use helm::PtxtType;
 
 #[test]
 fn parse_two_bit_adder() {
@@ -42,10 +43,81 @@ fn input_wires_arithmetic_parser() {
     }
 }
 
-// Check that it crashes if it contains both LUTs and arithmetic.
+/// Check that it crashes if it contains both LUTs and arithmetic.
 #[test]
 #[should_panic(expected = "Can't mix LUTs with arithmetic operators!")]
 fn invalid_arithmetic_with_luts_parser() {
     let (_, _, _, _, _, _, _) =
         read_verilog_file("hdl-benchmarks/processed-netlists/invalid.v", true);
 }
+
+/// Test get_input_wire_map with true, false, 0, 1 for bool.
+///     wire, value
+///     a[0], true
+///     a[1], 0
+///     b[0], false
+///     b[1], 1
+///     cin, false
+#[test]
+fn bool_input_wires() {
+    let wire_map = read_input_wires("./hdl-benchmarks/test-cases/2-bit-adder.inputs.csv", "bool");
+
+    assert_eq!(wire_map["a[0]"], PtxtType::Bool(true));
+    assert_eq!(wire_map["a[1]"], PtxtType::Bool(false));
+    assert_eq!(wire_map["b[0]"], PtxtType::Bool(false));
+    assert_eq!(wire_map["b[1]"], PtxtType::Bool(true));
+    assert_eq!(wire_map["cin"], PtxtType::Bool(false));
+}
+
+/// Test get_input_wire_map with integer.
+///     wire, value
+///     N0, 2
+///     N1, 7
+///     N2, 9
+#[test]
+fn integer_input_wires() {
+    let wire_map = read_input_wires(
+        "./hdl-benchmarks/test-cases/chi_squared_arith_1.inputs.csv",
+        "u8",
+    );
+    assert_eq!(wire_map["N0"], PtxtType::U8(2));
+    assert_eq!(wire_map["N1"], PtxtType::U8(7));
+    assert_eq!(wire_map["N2"], PtxtType::U8(9));
+
+    let wire_map = read_input_wires(
+        "./hdl-benchmarks/test-cases/chi_squared_arith_1.inputs.csv",
+        "u16",
+    );
+    assert_eq!(wire_map["N0"], PtxtType::U16(2));
+    assert_eq!(wire_map["N1"], PtxtType::U16(7));
+    assert_eq!(wire_map["N2"], PtxtType::U16(9));
+
+    let wire_map = read_input_wires(
+        "./hdl-benchmarks/test-cases/chi_squared_arith_1.inputs.csv",
+        "u32",
+    );
+    assert_eq!(wire_map["N0"], PtxtType::U32(2));
+    assert_eq!(wire_map["N1"], PtxtType::U32(7));
+    assert_eq!(wire_map["N2"], PtxtType::U32(9));
+
+    let wire_map = read_input_wires(
+        "./hdl-benchmarks/test-cases/chi_squared_arith_1.inputs.csv",
+        "u64",
+    );
+    assert_eq!(wire_map["N0"], PtxtType::U64(2));
+    assert_eq!(wire_map["N1"], PtxtType::U64(7));
+    assert_eq!(wire_map["N2"], PtxtType::U64(9));
+
+    let wire_map = read_input_wires(
+        "./hdl-benchmarks/test-cases/chi_squared_arith_1.inputs.csv",
+        "u128",
+    );
+    assert_eq!(wire_map["N0"], PtxtType::U128(2));
+    assert_eq!(wire_map["N1"], PtxtType::U128(7));
+    assert_eq!(wire_map["N2"], PtxtType::U128(9));
+}
+
+// TODO:
+/// Test get_input_wire_map with int for bits (AES example).
+#[test]
+fn bool_input_wires_array_as_int() {}