Fix caching for arithmetic circuits and add test

Co-authored-by: Dimitris Mouris <[email protected]>
TrustworthyComputing · Aug 29, 2023 · 7363508 · 7363508
1 parent 3eec928
commit 7363508
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Showing 3 changed files with 277 additions and 48 deletions.
diff --git a/src/bin/helm.rs b/src/bin/helm.rs
@@ -102,16 +102,8 @@ fn main() {
         let (gates_set, wire_map_im, input_wires, output_wires, dff_outputs, _, _) =
             verilog_parser::read_verilog_file(&file_name, true, arithmetic_type);
         let mut circuit_ptxt =
-            circuit::Circuit::new(gates_set.clone(), &input_wires, &output_wires, &dff_outputs);
+            circuit::Circuit::new(gates_set, &input_wires, &output_wires, &dff_outputs);
 
-        // TODO(@cgouert): move this check in the parser (and the same for gates/luts)
-        if gates_set.is_empty() {
-            panic!(
-                "{}[!]{} Parser error, no arithmetic gates detected.",
-                color::Fg(color::LightRed),
-                color::Fg(color::Reset)
-            );
-        }
         circuit_ptxt.sort_circuit();
         circuit_ptxt.compute_levels();
         #[cfg(debug_assertions)]
@@ -163,22 +155,14 @@ fn main() {
             verilog_parser::read_verilog_file(&file_name, false, arithmetic_type);
         let is_sequential = dff_outputs.len() > 1;
         let mut circuit_ptxt =
-            circuit::Circuit::new(gates_set.clone(), &input_wires, &output_wires, &dff_outputs);
+            circuit::Circuit::new(gates_set, &input_wires, &output_wires, &dff_outputs);
         if num_cycles > 1 && !is_sequential {
             panic!(
                 "{}[!]{} Cannot run combinational circuit for more than one cycles.",
                 color::Fg(color::LightRed),
                 color::Fg(color::Reset)
             );
         }
-        if gates_set.is_empty() {
-            panic!(
-                "{}[!]{} Parser error, no gates detected. Make sure to use the \
-                    'no-expr' flag in Yosys.",
-                color::Fg(color::LightRed),
-                color::Fg(color::Reset)
-            );
-        }
         circuit_ptxt.sort_circuit();
         circuit_ptxt.compute_levels();
         #[cfg(debug_assertions)]