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Add copy gate for arithmetic mode
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cgouert committed Sep 6, 2023
1 parent b23ba93 commit 747cdf3
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Showing 4 changed files with 32 additions and 1 deletion.
2 changes: 1 addition & 1 deletion hdl-benchmarks
5 changes: 5 additions & 0 deletions src/circuit.rs
Original file line number Diff line number Diff line change
Expand Up @@ -892,6 +892,11 @@ impl<'a> EvalCircuit<FheType> for ArithCircuit<'a> {
&input_values[1],
cycle,
false)
} else if gate.get_gate_type() == GateType::Copy {
gate.evaluate_encrypted_copy_block(
&input_values[0],
cycle,
)
} else {
gate.evaluate_encrypted_mul_block(
&input_values[0],
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19 changes: 19 additions & 0 deletions src/gates.rs
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@ pub enum GateType {
Div, // div ID(in0, in1, out);
Shl, // shl ID(in0, in1, out);
Shr, // shr ID(in0, in1, out);
Copy, // copy ID(in, out);
}

#[derive(Clone)]
Expand Down Expand Up @@ -180,6 +181,7 @@ impl Gate {
GateType::Sub => unreachable!(),
GateType::Shl => unreachable!(),
GateType::Shr => unreachable!(),
GateType::Copy => unreachable!(),
GateType::Mux => match (&input_values[2], &input_values[0], &input_values[1]) {
(PtxtType::Bool(select), PtxtType::Bool(in_0), PtxtType::Bool(in_1)) => {
PtxtType::Bool((*select && *in_0) || (!select && *in_1))
Expand Down Expand Up @@ -255,6 +257,7 @@ impl Gate {
GateType::Sub => panic!("Sub gates can't be mixed with Boolean ops!"),
GateType::Shl => panic!("Left shifts can't be mixed with Boolean ops!"),
GateType::Shr => panic!("Right shifts can't be mixed with Boolean ops!"),
GateType::Copy => panic!("Arithmetic copies can't be mixed with Boolean ops!"),
GateType::Mux => server_key.mux(&input_values[2], &input_values[0], &input_values[1]),
GateType::Nand => server_key.nand(&input_values[0], &input_values[1]),
GateType::Nor => server_key.nor(&input_values[0], &input_values[1]),
Expand Down Expand Up @@ -290,6 +293,22 @@ impl Gate {
ret
}

pub fn evaluate_encrypted_copy_block(
&mut self,
ct1: &FheType,
cycle: usize,
) -> FheType {
if self.cycle == cycle {
match self.encrypted_multibit_output {
FheType::None => (),
_ => return self.encrypted_multibit_output.clone(),
}
}
self.encrypted_multibit_output = ct1.clone();
self.cycle = cycle;
self.encrypted_multibit_output.clone()
}

pub fn evaluate_encrypted_mul_block(
&mut self,
ct1: &FheType,
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7 changes: 7 additions & 0 deletions src/verilog_parser.rs
Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,7 @@ fn parse_gate(tokens: &[&str]) -> Gate {
"sub" => GateType::Sub,
"shl" => GateType::Shl,
"shr" => GateType::Shr,
"copy" => GateType::Copy,
_ => panic!("Invalid gate type \"{}\"", tokens[0]),
};

Expand Down Expand Up @@ -79,6 +80,11 @@ fn parse_gate(tokens: &[&str]) -> Gate {
let output_wire = String::from(extract_const_val(tokens[1]));
(vec![], output_wire)
}
GateType::Copy => {
let input_wires = vec![String::from(name_and_inputs[1])];
let output_wire = String::from(tokens[2].trim_end_matches(';').trim_end_matches(')'));
(input_wires, output_wire)
}
_ => {
let mut input_wires = vec![String::from(name_and_inputs[1])];
input_wires.push(tokens[2].trim_end_matches(',').trim().to_owned());
Expand Down Expand Up @@ -225,6 +231,7 @@ pub fn read_verilog_file(
|| gate.get_gate_type() == GateType::Div
|| gate.get_gate_type() == GateType::Shl
|| gate.get_gate_type() == GateType::Shr
|| gate.get_gate_type() == GateType::Copy
{
has_arith = true;
}
Expand Down

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