Single_button
Button, which requires a single input FPGA.
IMPORTANT. When reading from the buttons required buffering / input processing, otherwise it may be a signal line, characterized by 0 or 1, leading to errors in the modules which will cause very difficult to understand (Z-state of input).
IMPORTANT2. Inverted input: if the button is pressed, the result is 0.
Example.
//3bit buffer
reg [2:0] gate_buff;
always @ (posedge clk50M)
gate_buff <= {gate_buff[1:0],~key0};
//buffered value
assign GATE_D = (gate_buff == 3'b111);
//pos edge
assign GATE_POSEDGE = (gate_buff == 3'b011);
//neg adge
assign GATE_NEGEDGE = (gate_buff == 3'b110);