Ria - RIsc-v processor with Approximate execution units

UM-SJTU JI VE450 2021 Summer Capstone Design Project 33

Advisor: Dr. Weikang Qian

Team: Zhiyuan Liu, Jian Shi, Li Shi, Yiqiu Sun, Yichao Yuan

Resources

Tutorials

1. SystemVerilog tutorials, Link

Open source RISC-V cores

1. The Berkeley Out-of-Order Machine (BOOM), Docs, GitHub

2. Rocket-chip, GitHub

3. HIT MIPS Core, GitHub

4. Hummingbirdv2 E203 Core and SoC, Docs

5. EH1 RISC-V SweRV Core from WD, GitHub

6. RSD, GitHub

Xilinx IP cores

1. Floating point operator, IP

2. Multiplier, IP

3. Divider, IP

4. Block memory generator, IP