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148 changes: 148 additions & 0 deletions
148
tools/Vitis-AI-Runtime/VART/target_factory/targets/DPUCVDX8G_ISA0_B4096C16B1_DW_QT.prototxt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,148 @@ | ||
| # Copyright 2019 Xilinx Inc. | ||
| # | ||
| # Licensed under the Apache License, Version 2.0 (the "License"); | ||
| # you may not use this file except in compliance with the License. | ||
| # You may obtain a copy of the License at | ||
| # | ||
| # http://www.apache.org/licenses/LICENSE-2.0 | ||
| # | ||
| # Unless required by applicable law or agreed to in writing, software | ||
| # distributed under the License is distributed on an "AS IS" BASIS, | ||
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| # See the License for the specific language governing permissions and | ||
| # limitations under the License. | ||
|
|
||
| name: "DPUCVDX8G_ISA0_B4096C16B1_DW_QT" | ||
| type: "DPUCVDX8G" | ||
| isa_version: 0x00 | ||
| feature_code: 0x0004f2022210 | ||
| bank_group { | ||
| name: "VB0" | ||
| type: "Virtual" | ||
| base_id: 0 | ||
| bank_num: 8 | ||
| bank_width: 16 | ||
| bank_depth: 4096 | ||
| } | ||
| bank_group { | ||
| name: "VB1" | ||
| type: "Virtual" | ||
| base_id: 8 | ||
| bank_num: 8 | ||
| bank_width: 16 | ||
| bank_depth: 4096 | ||
| } | ||
| bank_group { | ||
| name: "CONVW" | ||
| type: "Param" | ||
| base_id: 16 | ||
| bank_num: 16 | ||
| bank_width: 16 | ||
| bank_depth: 4096 | ||
| } | ||
| bank_group { | ||
| name: "DWCONVW" | ||
| type: "Param" | ||
| base_id: 32 | ||
| bank_num: 1 | ||
| bank_width: 16 | ||
| bank_depth: 4096 | ||
| } | ||
| bank_group { | ||
| name: "BIAS" | ||
| type: "Param" | ||
| base_id: 33 | ||
| bank_num: 1 | ||
| bank_width: 16 | ||
| bank_depth: 2048 | ||
| } | ||
| bank_group { | ||
| name: "DWCVBIAS" | ||
| type: "Param" | ||
| base_id: 34 | ||
| bank_num: 1 | ||
| bank_width: 16 | ||
| bank_depth: 2048 | ||
| } | ||
| load_engine { | ||
| channel_parallel: 16 | ||
| output_bank: "VB0" | ||
| output_bank: "VB1" | ||
| } | ||
| save_engine { | ||
| channel_parallel: 16 | ||
| input_bank: "VB0" | ||
| input_bank: "VB1" | ||
| } | ||
| conv_engine { | ||
| input_channel_parallel: 16 | ||
| output_channel_parallel: 16 | ||
| pixel_parallel: 8 | ||
| input_bank: "VB0" | ||
| input_bank: "VB1" | ||
| output_bank: "VB0" | ||
| output_bank: "VB1" | ||
| weight_bank: "CONVW" | ||
| bias_bank: "BIAS" | ||
| nonlinear { | ||
| nonlinear_type: relu | ||
| nonlinear_type: leaky_relu | ||
| nonlinear_type: relu_six | ||
| } | ||
| conv_limit { | ||
| kernel_size: "1-16" | ||
| stride: "1-8" | ||
| } | ||
| } | ||
| eltwise_engine { | ||
| channel_parallel: 16 | ||
| pixel_parallel: 2 | ||
| input_bank: "VB0" | ||
| input_bank: "VB1" | ||
| output_bank: "VB0" | ||
| output_bank: "VB1" | ||
| nonlinear { | ||
| nonlinear_type: relu | ||
| } | ||
| elew_type: add | ||
| } | ||
| pool_engine { | ||
| channel_parallel: 16 | ||
| pixel_parallel: 2 | ||
| input_bank: "VB0" | ||
| input_bank: "VB1" | ||
| output_bank: "VB0" | ||
| output_bank: "VB1" | ||
| nonlinear { | ||
| nonlinear_type: relu | ||
| } | ||
| pool_type: max | ||
| max_limit { | ||
| kernel_size: "1-8" | ||
| stride: "1-4" | ||
| } | ||
| pool_type: avg | ||
| avg_limit { | ||
| kernel_size: "2-8" | ||
| stride: "1-4" | ||
| } | ||
| } | ||
| dwconv_engine { | ||
| channel_parallel: 16 | ||
| pixel_parallel: 2 | ||
| input_bank: "VB0" | ||
| input_bank: "VB1" | ||
| output_bank: "VB0" | ||
| output_bank: "VB1" | ||
| weight_bank: "DWCONVW" | ||
| bias_bank: "DWCVBIAS" | ||
| nonlinear { | ||
| nonlinear_type: relu | ||
| nonlinear_type: relu_six | ||
| } | ||
| dwconv_limit { | ||
| kernel_size: "1-16" | ||
| stride: "1-4" | ||
| } | ||
| } | ||
| batch: 1 |
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