See Vitis™ Development Environment on xilinx.com |
The AI Engine Development Feature Tutorials highlight specific features and flows that help develop AI Engine applications.
The README of AI Engine Development contains important information including tool version, environment settings, and a table describing the platform, operating system, and supported features or flows of each tutorial. It is strongly recommended that you review details before starting to use the AIE tutorials.
| Tutorial | Description |
| AI Engine A-to-Z Flow for Linux | This tutorial intoduces a platform-based approach to develop the adaptable subsystem that contains PL kernels and AI Engine graph, demonstrates how you can quickly validate the design by means of hardware emulation or hardware using the base platform, and quickly switch to the custom platform with minimal changes. |
| A to Z Bare-metal Flow | This tutorial walks through the steps to create a custom Baremetal platform, and also integrate Baremetal host application along with an AI Engines graph and PL kernels. |
| Using GMIO with AIE | This tutorial introduces the usage of global memory I/O (GMIO) for sharing data between the AI Engines and external DDR |
| Runtime Parameter Reconfiguration | Learn how to dynamically update AI Engine runtime parameters |
| Packet Switching | This tutorial illustrates how to use data packet switching with AI Engine designs to optimize efficiency. |
| AI Engine Versal Integration for Hardware Emulation and Hardware | This tutorial demonstrates creating a system design running on the AI Engine, PS, and PL and validating the design running on these heterogeneous domains by running Hardware Emulation. |
| Versal System Design Clocking | This tutorial demonstrates clocking concepts for the Vitis compiler by defining clocking for ADF graph PL kernels and PLIO kernels, using the clocking automation functionality. |
| Using Floating-Point in the AI Engine | These examples demonstrate floating-point vector computations in the AI Engine. |
| DSP Library Tutorial | This tutorial demonstrates how to use kernels provided by the DSP library for a filtering application, how to analyze the design results, and how to use filter parameters to optimize the design's performance using simulation. |
| Debug Walkthrough Tutorial | This tutorial demonstrates how to debug a multi-processor application using the Versal ACAP AI Engines, using a beamformer example design. The tutorial illustrates functional debug and performance level debug techniques. |
| AI Engine DSP Library and Model Composer Tutorial | This tutorial shows how to design AI Engine applications using Model Composer. This set of blocksets for Simulink is used to demonstrate how easy it is to develop applications for Xilinx devices, integrating RTL/HLS blocks for the Programmable Logic, as well as AI Engine blocks for the AI Engine array. |
| Versal Emulation Waveform Analysis | This tutorial demonstrates how you can use the Vivado logic simulator (XSIM) waveform GUI, and the Vitis analyzer to debug and analyze your design for a Versal ACAP. |
| AXIS External Traffic Generator | This tutorial shows how to use AXI Traffic Generators to provide input and capture output from an AI Engine kernel in hardware emulation. |
| AI Engine Performance and Deadlock Analysis Tutorial | This tutorial introduces you to performance analysis and optimization methods, and shows you how synchronization works in graph execution. It also demonstrates the analysis of a hang issue using an example. |
| Implementing an IIR Filter on the AI Engine | This multi-part tutorial describes how to implement an [infinite impulse response (IIR) filter](https://en.wikipedia.org/wiki/Infinite_impulse_response) on the AI Engine. |
| Post-Link Recompile of an AI Engine Application | This tutorial shows you how to modify an AI Engine application after the platform has been frozen. It avoids a complete Vivado® tool run, which can take a long time if timing closure requires specific attention. The only limitation is that the hardware connection between the AI Engine array and the programmable logic (PL) must be kept fixed. The tutorial demonstrates a Vitis IDE flow and a Makefile flow. |
| Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows | This tutorial develops a case in which the dataflow goes back and forth multiple times between the programmable logic (PL) and the AI Engine array. Some PL blocks are only source or destination kernels, whereas others are processing kernels within the dataflow. This tutorial demonstrates how to create external traffic generators as Python scripts or C++ applications to exercise the AI Engine kernels in the x86 simulator, AI Engine simulator, and in hardware emulation. |
| Using RTL IP with AI Engines | This tutorial demonstrates how to reuse any AXI-based IP you have created as an RTL IP, control your platform, and convert your RTL IP to an RTL kernel allowing for a more streamlined process for creating the design you need. |
| Using Verilog Traffic Generators in AIE Simulation | This tutorial demonstrates how to use Verilog or System Verilog modules to drive traffic in and out of an ADF graph running in the AIE Simulator. |
| AIE Compiler Features | This tutorial shares a variety of features that are useful for AI Engine / AI Engine-ML (AIE-ML) programming to create more visible and efficient code compared to early versions of the compiler. |
| Two Tone Filter on AIE Using DSP libraries and Vitis Model Composer | This tutorial demonstrates how to implement the same MATLAB model design using the Vitis DSP libraries targeting AI Engine. This MATLAB model design, which has a two tone input signal. The FIR suppresses 1-tone from a 2-tone input signal. The output of the FIR filter connects to the FFT block. This FFT block acts as a monitor to display a spectrum plot. This tutorial has four parts. In part 1, the sampling rate requirement is 400 Msps; in part 2, the sampling rate requirement is 2000 Msps, in part 3, implement the part 1 design using Vitis IDE and then finally, in part4, implement the part 1 design using Vitis Model Composer tool. |
| Performance Validation in Analysis View of the Vitis Unified IDE | This tutorial demonstrates throughput and latency computation after AI Engine Simulation and their analysis in the Analysis View of the Vitis Unified IDE. |
| RTL / AI Engine interfacing Examples | This tutorial shows ways of interfacing user RTL logic to the AI Engine using the Vitis acceleration flow. |
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