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Merge pull request #925 from Xilinx/feature/dwc
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DWC RTL variant
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@auphelia
auphelia authored Nov 28, 2023
2 parents 8f9f10c + 9edcdc6 commit d980f7c
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158 changes: 158 additions & 0 deletions finn-rtllib/dwc/hdl/dwc.sv
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/******************************************************************************
* Copyright (C) 2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* @brief Stream Data Width Converter.
* @author Thomas B. Preußer <[email protected]>
*****************************************************************************/
module dwc #(
int unsigned IBITS,
int unsigned OBITS
)(
//- Global Control ------------------
input logic clk,
input logic rst,

//- AXI Stream - Input --------------
output logic irdy,
input logic ivld,
input logic [IBITS-1:0] idat,

//- AXI Stream - Output -------------
input logic ordy,
output logic ovld,
output logic [OBITS-1:0] odat
);

if(IBITS == OBITS) begin : genNoop
assign irdy = ordy;
assign ovld = ivld;
assign odat = idat;
end : genNoop
else if(IBITS < OBITS) begin : genUp

// Sanity Checking: integer upscaling
initial begin
if(OBITS % IBITS) begin
$error("Output width %0d is not a multiple of input width %0d.", OBITS, IBITS);
$finish;
end
end

// Parallelizing Shift Register A and Sidestep Buffer B on Input Path
localparam int unsigned K = OBITS / IBITS;
typedef logic [IBITS-1:0] dat_t;
dat_t [K-1:0] ADat = 'x;
logic [$clog2(K):0] ACnt = K-1; // (empty) K-1, ..., 0, -1 (full/valid)
dat_t BDat = 'x;
logic BRdy = 1;
always_ff @(posedge clk) begin
if(rst) begin
ADat <= 'x;
ACnt <= K-1;
BDat <= 'x;
BRdy <= 1;
end
else begin
automatic type(ACnt) acnt = (ovld && ordy)? K-1 : ACnt;
automatic logic rdy = !ovld || ordy;
if((ivld || !BRdy) && rdy) begin
ADat <= { BRdy? idat : BDat, ADat[K-1:1] };
acnt--;
end
ACnt <= acnt;

if(BRdy) BDat <= idat;
BRdy <= rdy || (BRdy && !ivld);
end
end

// Output Assignments
assign irdy = BRdy;
assign ovld = ACnt[$left(ACnt)];
assign odat = ADat;

end : genUp
else begin : genDown

// Sanity Checking: integer downscaling
initial begin
if(IBITS % OBITS) begin
$error("Input width %0d is not a multiple of output width %0d.", IBITS, OBITS);
$finish;
end
end

// Serializing Shift Register A and Sidestep Buffer B on Output Path
localparam int unsigned K = IBITS / OBITS;
typedef logic [OBITS-1:0] dat_t;
dat_t [ K-1:0] ADat = 'x;
logic [$clog2(K):0] ACnt = 1; // (full) -K+1, ..., -1, 0, 1 (empty/not valid)
dat_t BDat = 'x;
logic BRdy = 1;
dat_t CDat = 'x;
logic CVld = 0;
always_ff @(posedge clk) begin
if(rst) begin
ADat <= 'x;
ACnt <= 1;
BDat <= 'x;
BRdy <= 1;
CDat <= 'x;
CVld <= 0;
end
else begin
automatic type(ACnt) acnt = ACnt;
automatic logic ainc = 0;
if(irdy) begin
ADat <= idat;
acnt = ivld? -K+1 : 1;
end
else if(BRdy) begin
ADat <= { {OBITS{1'bx}}, ADat[K-1:1] };
ainc = BRdy;
end;
ACnt <= acnt + ainc;

if(BRdy) BDat <= ADat[0];
BRdy <= !CVld || ordy || (BRdy && !ACnt[$left(ACnt)] && ACnt[0]);

if(!CVld || ordy) CDat <= BRdy? ADat[0] : BDat;
CVld <= (CVld && !ordy) || !BRdy || ACnt[$left(ACnt)] || !ACnt[0];
end
end

// Output Assignments
assign irdy = BRdy && !ACnt[$left(ACnt)];
assign ovld = CVld;
assign odat = CDat;

end : genDown

endmodule : dwc
65 changes: 65 additions & 0 deletions finn-rtllib/dwc/hdl/dwc_axi.sv
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/******************************************************************************
* Copyright (C) 2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* @brief AXI Stream Adapter for Data Width Converter.
* @author Thomas B. Preußer <[email protected]>
*****************************************************************************/
module dwc_axi #(
int unsigned IBITS,
int unsigned OBITS,

localparam int unsigned AXI_IBITS = (IBITS+7)/8 * 8,
localparam int unsigned AXI_OBITS = (OBITS+7)/8 * 8
)(
//- Global Control ------------------
input logic ap_clk,
input logic ap_rst_n,

//- AXI Stream - Input --------------
output logic s_axis_tready,
input logic s_axis_tvalid,
input logic [AXI_IBITS-1:0] s_axis_tdata,

//- AXI Stream - Output -------------
input logic m_axis_tready,
output logic m_axis_tvalid,
output logic [AXI_OBITS-1:0] m_axis_tdata
);

dwc #(.IBITS(IBITS), .OBITS(OBITS)) core (
.clk(ap_clk), .rst(!ap_rst_n),
.irdy(s_axis_tready), .ivld(s_axis_tvalid), .idat(s_axis_tdata[IBITS-1:0]),
.ordy(m_axis_tready), .ovld(m_axis_tvalid), .odat(m_axis_tdata[OBITS-1:0])
);
if(OBITS < AXI_OBITS) begin
assign m_axis_tdata[AXI_OBITS-1:OBITS] = '0;
end

endmodule : dwc_axi
71 changes: 71 additions & 0 deletions finn-rtllib/dwc/hdl/dwc_template.v
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/******************************************************************************
* Copyright (C) 2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/

module $TOP_MODULE_NAME$ #(
parameter IBITS = $IBITS$,
parameter OBITS = $OBITS$,

parameter AXI_IBITS = (IBITS+7)/8 * 8,
parameter AXI_OBITS = (OBITS+7)/8 * 8
)(
//- Global Control ------------------
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *)
input ap_clk,
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input ap_rst_n,

//- AXI Stream - Input --------------
output in0_V_TREADY,
input in0_V_TVALID,
input [AXI_IBITS-1:0] in0_V_TDATA,

//- AXI Stream - Output -------------
input out_V_TREADY,
output out_V_TVALID,
output [AXI_OBITS-1:0] out_V_TDATA
);

dwc_axi #(
.IBITS(IBITS),
.OBITS(OBITS)
) impl (
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.s_axis_tready(in0_V_TREADY),
.s_axis_tvalid(in0_V_TVALID),
.s_axis_tdata(in0_V_TDATA),
.m_axis_tready(out_V_TREADY),
.m_axis_tvalid(out_V_TVALID),
.m_axis_tdata(out_V_TDATA)
);

endmodule
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