Trying to use block ram

[zaun]

I'm trying to use block ram on a Gowin FPGA... When I try to synthesize with yosys -q -p "read_verilog -sv src/soc_simple.sv; synth_gowin -top top -json synthesis.json" I get the following errors:

/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:209: Warning: Range [7:0] select out of bounds on signal `\PORT_A_WR_DATA': Setting 7 MSB bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:209: Warning: Range select [16:9] out of bounds on signal `\PORT_A_WR_DATA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:209: Warning: Range select [25:18] out of bounds on signal `\PORT_A_WR_DATA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:209: Warning: Range select [34:27] out of bounds on signal `\PORT_A_WR_DATA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:210: Warning: Range [7:0] select out of bounds on signal `\PORT_B_WR_DATA': Setting 7 MSB bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:210: Warning: Range select [16:9] out of bounds on signal `\PORT_B_WR_DATA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:210: Warning: Range select [25:18] out of bounds on signal `\PORT_B_WR_DATA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:210: Warning: Range select [34:27] out of bounds on signal `\PORT_B_WR_DATA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:214: Warning: Range select [23:16] out of bounds on signal `\genblk1.DOA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:214: Warning: Range select [31:24] out of bounds on signal `\genblk1.DOA': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:215: Warning: Range select [23:16] out of bounds on signal `\genblk1.DOB': Setting all 8 result bits to undef.
/Users/justinzaun/local/brew/bin/../share/yosys/gowin/brams_map.v:215: Warning: Range select [31:24] out of bounds on signal `\genblk1.DOB': Setting all 8 result bits to undef.

My block ram is simple...

`timescale 1ns / 1ps
`default_nettype none

`include "src/log.sv"

module block_ram #(
    parameter int SIZE  = 1024,
    parameter int WIDTH = 8
) (
	input  wire         						clk,
	input  wire         						reset,
	input  wire         						write_en,
	input  wire [$clog2(SIZE/(WIDTH/8)) - 1:0]  write_address,
	input  wire [WIDTH-1:0]   					write_data,
	input  wire [$clog2(SIZE/(WIDTH/8)) - 1:0]  read_address,
	output reg  [WIDTH-1:0]   					read_data
);

initial begin
    `ASSERT((WIDTH >= 8), "WIDTH must be at least 8 bits.");
    `ASSERT((WIDTH % 8 == 0), "WIDTH must be divisible by 8 to ensure byte alignment.");
    `ASSERT((SIZE % (WIDTH / 8) == 0), "SIZE must be a multiple of WIDTH/8 to ensure proper byte alignment.");
end

(* ram_style = "block" *)
reg [WIDTH-1:0] memory[(SIZE/(WIDTH/8)) - 1:0];

always @(posedge clk or posedge reset) begin
	if (reset) begin
		read_data <= 0;
	end else begin
		read_data <= memory[read_address];
	end
end

always @(posedge clk) begin
	if (write_en) begin
		memory[write_address] <= write_data;
	end
end
endmodule

I'm using SIZE of 1024 and WIDTH of 8. But I've tried 8, 16 and 32 for WIDTH and they all end up the same. Any idea what I'm doing wrong?

yosys --version
Yosys 0.48 (git sha1 aaa5347, clang++ 16.0.0 -fPIC -O3)

[zaun]

I've updated to 0.49 and have the same issue.