Feat/word addressable memory

[moodlezoup]

Implements "word-addressable" memory for Jolt.

The RISC-V VM spec itself doesn't disallow access to unaligned memory addresses, but notes that implementations may only support aligned memory accesses. In this PR, we add constraints to enforce aligned loads/stores. This allows us to replace halfword and byte loads/stores (i.e. SB, SH, LB, LBU, LH, LHU) with "virtual sequences" (similar to those we use for division/remainder instructions) which emulate their behavior using a combination of bitops and SW/LW.

This improves prover performance and simplifies the code significantly.

Will update docs in a follow-up PR.

[wiz-a16z]

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