Merge branch 'develop'

.gitignore

@@ -69,13 +69,3 @@ ipch/
 # NuGet v3's project.json files produces more ignoreable files
 *.nuget.props
 *.nuget.targets
-
-TestAppLPC2387+IP175CD/settings/
-TestAppLPC2387+IP175CD/_Debug
-*.dep
-*.ewt
-/TestAppTM4C129+88E6352/Executable_1 clang Debug
-/TestAppTM4C129+88E6352/Executable_1 gcc Debug
-/TestAppTM4C129+88E6352/Executable_1 clang Release
-/TestAppTM4C129+88E6352/Executable_1 gcc Release
-*.hzs

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "edge"]
+	path = simulator/edge
+	url = https://github.com/adigostin/edge.git

README.md

@@ -16,27 +16,27 @@ The Simulator lets you create networks and see the library
 in action. See the screenshot below. This is a project for
 Visual Studio 2017.
 
-### Embedded Application Example
-The repository includes sources for a sample RSTP implementation
-on an embedded device: a project for IAR Embedded Workbench 7.x,
-for a device with an LPC2000 microcontroller and an IP175C
-switch chip.
+### Embedded Application Examples
+The repository includes sources with a couple of RSTP implementations
+on embedded devices with microcontrollers and switches such as
+Marvell, Microchip, IC+. The projects are for Rowley CrossWorks
+(gcc and clang compilers) and IAR Embedded Workbench (EDG compiler).
 
-This sample highlights the platform-specific
+These samples highlight the platform-specific
 code required by STP -- mostly code that writes to
 a few hardware registers of the switch chip. To integrate
 the library in your embedded application, you'll need to
 write platform-specific code for your particular switch IC.
 Drop me a message at
 [[email protected]](mailto:[email protected])
-and I'll try to help.
+and I might be able to help.
 
 ### API Help
 The repository also includes
 [help files](https://github.com/adigostin/mstp-lib/tree/master/_help)
 for most of the library APIs -
 [some](http://htmlpreview.github.io/?https://github.com/adigostin/mstp-lib/blob/master/_help/STP_CreateBridge.html)
-[quite](http://htmlpreview.github.io/?https://github.com/adigostin/mstp-lib/blob/master/_help/StpCallback_TransmitGetBuffer.html)
+[rather](http://htmlpreview.github.io/?https://github.com/adigostin/mstp-lib/blob/master/_help/StpCallback_TransmitGetBuffer.html)
 [extensive](http://htmlpreview.github.io/?https://github.com/adigostin/mstp-lib/blob/master/_help/STP_OnPortEnabled.html).
 
 ### Screenshot of the Windows Simulator

TestAppLPC2387+IP175CD/.gitignore

@@ -0,0 +1,3 @@
+settings
+_Debug
+*.dep

TestAppMK66F+KSZ8794/.gitignore

@@ -0,0 +1,2 @@
+/* THUMB Debug
+/*.hzs

TestAppMK66F+KSZ8794/TestAppMK66F+KSZ8794.hzp

@@ -0,0 +1,126 @@
+<!DOCTYPE CrossStudio_Project_File>
+<solution Name="TestAppMK66F+KSZ8794" target="8" version="2">
+  <project Name="TestAppMK66F+KSZ8794">
+    <configuration
+      CMSIS_CORE="Yes"
+      Name="Common"
+      Placement="Flash"
+      Target="MK66FN2M0xxx18"
+      arm_architecture="v7EM"
+      arm_core_type="Cortex-M4"
+      arm_fpu_type="FPv4-SP-D16"
+      arm_gcc_target="arm-unknown-eabi"
+      arm_linker_heap_size="0"
+      arm_linker_stack_size="4096"
+      arm_simulator_memory_simulation_filename="$(TargetsDir)/Kinetis/KinetisSimulatorMemory$(HostDLL)"
+      arm_simulator_memory_simulation_parameter="MK66FN2M0xxx18;0x200000;0x0;0x0;0x40000;4"
+      arm_target_debug_interface_type="ADIv5"
+      arm_target_loader_applicable_loaders="Flash"
+      arm_target_loader_default_loader="Flash"
+      arm_target_restrict_memory_accesses="Yes"
+      c_additional_options="-fms-extensions"
+      c_preprocessor_definitions="STP_USE_LOG=0"
+      c_user_include_directories="$(TargetsDir)/Kinetis.;$(SolutionDir)/../mstp-lib"
+      debug_initial_breakpoint_set_option="Never"
+      debug_register_definition_file="$(TargetsDir)/Kinetis/MK66F18_Peripherals.xml"
+      debug_startup_completion_point="main"
+      gcc_c_language_standard="c11"
+      gcc_cplusplus_language_standard="c++1z"
+      linker_memory_map_file="$(TargetsDir)/Kinetis/MK66FN2M0xxx18_MemoryMap.xml"
+      linker_printf_fp_enabled="No"
+      linker_scanf_character_group_matching_enabled="No"
+      linker_scanf_fp_enabled="No"
+      linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml"
+      macros="DeviceVectorsFile=MK66F18.vec"
+      project_directory=""
+      project_type="Executable"
+      property_groups_file_path="$(TargetsDir)/Kinetis/propertyGroups.xml"
+      target_connect_script="Connect()"
+      target_get_partname_script="GetPartName()"
+      target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)"
+      target_reset_script="Reset()"
+      target_script_file="$(TargetsDir)/Kinetis/Kinetis_Target.js"
+      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
+    <configuration
+      Name="Flash"
+      arm_target_flash_loader_file_path="$(TargetsDir)/Kinetis/Release/Loader.elf"
+      arm_target_flash_loader_type="LIBMEM RPC Loader"
+      arm_target_loader_can_lock_all="No"
+      arm_target_loader_can_lock_range="No"
+      arm_target_loader_can_unlock_all="No"
+      arm_target_loader_can_unlock_range="No"
+      arm_target_loader_parameter="4" />
+    <folder Name="System Files">
+      <file file_name="$(StudioDir)/source/thumb_crt0.s" />
+      <file file_name="$(TargetsDir)/Kinetis/Kinetis_Startup.s">
+        <configuration
+          Name="Common"
+          c_preprocessor_definitions="STARTUP_FROM_RESET" />
+      </file>
+      <file file_name="$(TargetsDir)/Kinetis/$(DeviceVectorsFile)" />
+    </folder>
+    <file file_name="main.cpp" />
+    <folder Name="drivers">
+      <file file_name="drivers/clock.cpp" />
+      <file file_name="drivers/clock.h" />
+      <file file_name="drivers/uart.cpp" />
+      <file file_name="drivers/uart.h" />
+      <file file_name="drivers/gpio.cpp" />
+      <file file_name="drivers/gpio.h" />
+      <file file_name="drivers/pit.cpp" />
+      <file file_name="drivers/pit.h" />
+      <file file_name="drivers/ethernet.cpp" />
+      <file file_name="drivers/ethernet.h" />
+      <file file_name="drivers/spi.cpp" />
+      <file file_name="drivers/spi.h" />
+      <file file_name="drivers/event_queue.cpp" />
+      <file file_name="drivers/event_queue.h" />
+      <file file_name="drivers/scheduler.cpp" />
+      <file file_name="drivers/scheduler.h" />
+      <file file_name="drivers/serial_console.cpp" />
+      <file file_name="drivers/serial_console.h" />
+    </folder>
+    <file file_name="switch.cpp" />
+    <file file_name="switch.h" />
+    <folder Name="mstp-lib">
+      <file file_name="../mstp-lib/stp.h" />
+      <folder Name="internal">
+        <file file_name="../mstp-lib/internal/stp.cpp" />
+        <file file_name="../mstp-lib/internal/stp_base_types.cpp" />
+        <file file_name="../mstp-lib/internal/stp_base_types.h" />
+        <file file_name="../mstp-lib/internal/stp_bpdu.cpp" />
+        <file file_name="../mstp-lib/internal/stp_bpdu.h" />
+        <file file_name="../mstp-lib/internal/stp_bridge.h" />
+        <file file_name="../mstp-lib/internal/stp_conditions_and_params.cpp" />
+        <file file_name="../mstp-lib/internal/stp_conditions_and_params.h" />
+        <file file_name="../mstp-lib/internal/stp_log.cpp" />
+        <file file_name="../mstp-lib/internal/stp_log.h" />
+        <file file_name="../mstp-lib/internal/stp_md5.cpp" />
+        <file file_name="../mstp-lib/internal/stp_md5.h" />
+        <file file_name="../mstp-lib/internal/stp_port.h" />
+        <file file_name="../mstp-lib/internal/stp_procedures.cpp" />
+        <file file_name="../mstp-lib/internal/stp_procedures.h" />
+        <file file_name="../mstp-lib/internal/stp_sm.h" />
+        <file file_name="../mstp-lib/internal/stp_sm_bridge_detection.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_l2g_port_receive.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_information.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_protocol_migration.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_receive.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_role_selection.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_role_transitions.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_state_transition.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_timers.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_port_transmit.cpp" />
+        <file file_name="../mstp-lib/internal/stp_sm_topology_change.cpp" />
+      </folder>
+    </folder>
+  </project>
+  <configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug" />
+  <configuration
+    Name="Debug"
+    c_preprocessor_definitions="DEBUG"
+    gcc_debugging_level="Level 3"
+    gcc_omit_frame_pointer="Yes"
+    gcc_optimization_level="None"
+    hidden="Yes" />
+</solution>

TestAppMK66F+KSZ8794/drivers/clock.cpp

@@ -0,0 +1,175 @@
+
+#include "clock.h"
+#include <CMSIS/MK66F18.h>
+#include <assert.h>
+
+static uint32_t external_clock_mhz;
+
+
+#undef SYSTEM_MCG_C5_VALUE
+#undef SYSTEM_MCG_C6_VALUE
+#undef SYSTEM_MCG_C9_VALUE
+#undef SYSTEM_SIM_CLKDIV2_VALUE
+
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x0C */
+#define SYSTEM_MCG_C6_VALUE 0x4CU /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
+#define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
+/* MCG_C11: PLLCS=0 */
+#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SIM_CLKDIV2: USBDIV=6,USBFRAC=1 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x0DU /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3,RAMSIZE=0 */
+
+void clock_init (uint32_t external_clock_mhz)
+{
+	::external_clock_mhz = external_clock_mhz;
+
+	// TODO: make code below reusable; it is now hardcoded for the Segger board
+
+    SIM->CLKDIV1 = (0 << 28)  // OUTDIV1=0, divide MCGOUTCLK by 1 to get the core/system clock
+	             | (7 << 24)  // OUTDIV2=7, divide MCGOUTCLK by 8 to get the bus clock
+	             | (2 << 20)  // OUTDIV3=
+	             | (5 << 16); // OUTDIV4=
+    SIM->SOPT2 = SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK | (1 << SIM_SOPT2_PLLFLLSEL_SHIFT); // PLL/FLL clock select: MCGPLLCLK clock
+
+    SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+    /* PORTA_PCR18: ISF=0,MUX=0 */
+    PORTA_PCR18 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+    if (((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U)
+    {
+        /* PORTA_PCR19: ISF=0,MUX=0 */
+        PORTA_PCR19 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+    }
+    MCG->SC = SYSTEM_MCG_SC_VALUE;                                                                                  /* Set SC (fast clock internal reference divider) */
+    MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+    OSC->CR = SYSTEM_OSC_CR_VALUE;                                                                                  /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+    MCG->C7 = SYSTEM_MCG_C7_VALUE;                                                                                  /* Set C7 (OSC Clock Select) */
+
+    MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+
+    if ((((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE)&MCG_C7_OSCSEL_MASK) == 0x00U))
+    {
+        while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U)
+        { /* Check that the oscillator is running */
+        }
+    }
+    // Check that the source of the FLL reference clock is the requested one.
+    if (SYSTEM_MCG_C1_VALUE & MCG_C1_IREFS_MASK)
+    {
+        while ((MCG->S & MCG_S_IREFST_MASK) == 0x00U)
+			;
+    }
+    else
+    {
+        while ((MCG->S & MCG_S_IREFST_MASK) != 0x00U)
+			;
+    }
+    MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+
+    /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+    MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+    MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t) ~(MCG_C6_PLLS_MASK);      /* Set C6 (PLL select, VCO divider etc.) */
+    if ((SYSTEM_MCG_C5_VALUE)&MCG_C5_PLLCLKEN_MASK)
+    {
+        MCG->C5 |= MCG_C5_PLLCLKEN_MASK; /* PLL clock enable in mode other than PEE or PBE */
+    }
+
+    MCG_C11 = SYSTEM_MCG_C11_VALUE; /* Set C11 (Select PLL used to derive MCGOUT */
+    MCG->C6 |= (MCG_C6_PLLS_MASK);  /* Set C6 (PLL select, VCO divider etc.) */
+
+	// Wait until PLL is locked
+    while ((MCG->S & MCG_S_LOCK0_MASK) == 0x00U)
+		;
+
+    MCG->C1 &= (uint8_t) ~(MCG_C1_CLKS_MASK);
+
+	// Wait until output of the PLL is selected.
+    while ((MCG->S & MCG_S_CLKST_MASK) != 0x0CU)
+		;
+
+	// Wait until output of the correct PLL is selected
+	while (MCG->S2 != SYSTEM_MCG_C11_VALUE)
+		;
+
+    SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+    SIM->CLKDIV3 = ((SIM->CLKDIV3) & (uint32_t)(~(SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK))) | ((SYSTEM_SIM_CLKDIV3_VALUE) & (SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK)); /* Selects the PLLFLL clock divider. */
+}
+
+struct clock_info
+{
+	void* peripheral_base_address;
+	volatile uint32_t* reg;
+	uint32_t bitmask;
+};
+
+static const clock_info clock_infos[] =
+{
+	{ PORTA, &SIM->SCGC5, SIM_SCGC5_PORTA_MASK },
+	{ PORTB, &SIM->SCGC5, SIM_SCGC5_PORTB_MASK },
+	{ PORTC, &SIM->SCGC5, SIM_SCGC5_PORTC_MASK },
+	{ PORTD, &SIM->SCGC5, SIM_SCGC5_PORTD_MASK },
+	{ PORTE, &SIM->SCGC5, SIM_SCGC5_PORTE_MASK },
+	{ PIT,   &SIM->SCGC6, SIM_SCGC6_PIT_MASK   },
+	{ SPI1,  &SIM->SCGC6, SIM_SCGC6_SPI1_MASK  },
+	{ ENET,  &SIM->SCGC2, SIM_SCGC2_ENET_MASK  },
+	{ nullptr, nullptr, 0 },
+};
+
+void clock_enable (void* peripheral_base_address)
+{
+	auto p = clock_infos;
+	while (p->peripheral_base_address != nullptr)
+	{
+		if (p->peripheral_base_address == peripheral_base_address)
+		{
+			*p->reg |= p->bitmask;
+			break;
+		}
+
+		p++;
+	}
+
+	assert (p->peripheral_base_address != nullptr); // not found in array - needs to be added
+
+	// Delay after an RCC peripheral clock enabling.
+	// TODO: wait as much as necessary
+	asm ("nop;nop;nop;nop;");
+	asm ("nop;nop;nop;nop;");
+	asm ("nop;nop;nop;nop;");
+	asm ("nop;nop;nop;nop;");
+
+	// Or maybe we should force a "clock reset"?
+}
+
+bool clock_enabled (void* peripheral_base_address)
+{
+	auto p = clock_infos;
+	while (p->peripheral_base_address != nullptr)
+	{
+		if (p->peripheral_base_address == peripheral_base_address)
+			return *p->reg & p->bitmask;
+
+		p++;
+	}
+
+	assert (p->peripheral_base_address != nullptr); // not found in array - needs to be added
+	return false;
+}
+

TestAppMK66F+KSZ8794/drivers/clock.h

@@ -0,0 +1,6 @@
+
+#include <stdint.h>
+
+void clock_init (uint32_t external_clock_mhz);
+void clock_enable (void* peripheral_base_address);
+bool clock_enabled (void* peripheral_base_address);