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University of Utah Senior Capstone Project focusing on the creation of Dataflow architecture accelerators for MLP, CNN, and DNN on AMD-XILINX FPGAs using Vitis-HLS, FINN, and Brevitas.

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UofUtah HLS CNN Acceleration

  • Dataflow Accelerators for deep convolutional neural networks via Vitis HLS and Finn compiler for AMD-Xilinx FPGAs.

ANN_MNIST

  • 3 Layer Multilayer Perceptron implemented in Vitis-HLS for MNIST hand written digit recongition. Fully Connected layers represented as Matrix-Vector Multiplication and each layer is fully pipelined and unrolled for maximum throughput and performance.

Lenet5_Notebooks:

  • Quantization Aware training for 5 layer CNN (Lenet5) implementation in Brevitas using 8 bit quantizations for inputs, weights, and activations. Train on MNIST handwritted digits dataset, export to onnx, apply transformations, export to FINN for Vitis-HLS acclerator generation and deploy on AMD Kria KV260 SOM for inference evalution via PYNQ.

-FPGA Folding: Adjust onnx nodes Screenshot

Screenshot

Resnet 50/18 Notebooks:

In progress.

Validation and Results: Deployed as PYNQ overlay on AMD Kria KV260 SOM.

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University of Utah Senior Capstone Project focusing on the creation of Dataflow architecture accelerators for MLP, CNN, and DNN on AMD-XILINX FPGAs using Vitis-HLS, FINN, and Brevitas.

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