add cmpxchg8b spec

airbus-seclab · Feb 4, 2015 · 5d92632 · 5d92632
1 parent 47ed1c5
commit 5d92632
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diff --git a/amoco/arch/x64/spec_ia32e.py b/amoco/arch/x64/spec_ia32e.py
@@ -741,6 +741,20 @@ def ia32_rdrand(obj,Mod,RM,data):
     obj.operands = [op1]
     obj.type = type_other
 
+@ispec_ia32("*>[ {0f}{c7} /1 ]", mnemonic = "CMPXCHG8B")
+def ia32_cmpxchg(obj,Mod,RM,data):
+    op2,data = getModRM(obj,Mod,RM,data)
+    if not op2._is_mem: raise InstructionError(obj)
+    op2.size = 64
+    REX = obj.misc['REX']
+    if REX:
+        W=REX[0]
+        if W==1:
+            obj.mnemonic = "CMXCHG16B"
+            op2.size = 128
+    obj.operands = [op2]
+    obj.type = type_data_processing
+
 @ispec_ia32("*>[ {0f}{1f} /0  ]", mnemonic = "NOP",     type=type_cpu_state)
 @ispec_ia32("*>[ {0f}{ae} /4  ]", mnemonic = "XSAVE",   type=type_cpu_state)
 @ispec_ia32("*>[ {0f}{ae} /5  ]", mnemonic = "LFENCE",  type=type_cpu_state)

diff --git a/amoco/arch/x86/spec_ia32.py b/amoco/arch/x86/spec_ia32.py
@@ -738,6 +738,14 @@ def ia32_rdrand(obj,Mod,RM,REG,data):
     obj.operands = [op2,op1]
     obj.type = type_data_processing
 
+@ispec_ia32("*>[ {0f}{c7} /1 ]", mnemonic = "CMPXCHG8B")
+def ia32_cmpxchg(obj,Mod,RM,data):
+    op2,data = getModRM(obj,Mod,RM,data)
+    if not op2._is_mem: raise InstructionError(obj)
+    op2.size = 64
+    obj.operands = [op2]
+    obj.type = type_data_processing
+
 @ispec_ia32("*>[ {0f}{1f} /0  ]", mnemonic = "NOP",     type=type_cpu_state)
 @ispec_ia32("*>[ {0f}{ae} /4  ]", mnemonic = "XSAVE",   type=type_cpu_state)
 @ispec_ia32("*>[ {0f}{ae} /5  ]", mnemonic = "LFENCE",  type=type_cpu_state)