Release v1.08

akospasztor · Apr 20, 2018 · 455935c · 455935c
2 parents 828341e + 056d48c
commit 455935c
Show file tree

Hide file tree

Showing 45 changed files with 35,757 additions and 1,985 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -0,0 +1,84 @@
+# Changelog for STM32 Bootloader
+
+## [Unreleased]
+- Check checksum of application found on SD card before programming
+- Switch to semantic versioning
+
+
+## [1.08](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.08) - 2018-04-18
+### Added
+- Verify flash content after programming
+- Introduced changelog file
+### Changed
+- The bootloader is now optimized for a new hardware. Due to new pinout of LEDs, user button and SD card switch, the appropriate defines have been changed in main.h file.
+- Bootloader sequence with richer error and debug messages
+- Updated SD card driver with DMA support
+- Project now uses IAR CMSIS pack
+- Updated STM32L4xx CMSIS to 1.4.2
+- Updated STM32L4xx HAL library to 1.8.2
+### Fixed
+- Changed appropriate variable types
+- Updated README and sequence graph
+- Updated header files
+
+
+## [1.07](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.07) - 2017-12-08
+### Added
+- SD card power on/off support
+### Changed
+- As a result of recent hardware changes introduced in a device that is developed as part of our ongoing projects, the SD card is now powered on/off with a FET controlled by the MCU to minimize energy consumption. Therefore, the SD card has to be manually powered on during initialization.
+
+
+## [1.06](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.06) - 2017-11-13
+### Added
+- Introduced RAM_SIZE define to precisely check whether the flash contains valid application upon startup
+### Fixed
+- CheckForApplication() function
+
+
+## [1.05](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.05) - 2017-10-30
+### Added
+- Application-specific configuration defines
+### Changed
+- Updated STM32L4xx CMSIS to 1.4.1
+- Updated STM32L4xx HAL library to 1.8.1
+
+
+## [1.04](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.04) - 2017-10-16
+### Added
+- Option to skip programming after flash erase operation
+### Changed
+- Better visual feedback when no application is found in flash
+### Fixed
+- General improvements
+
+
+## [1.03](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.03) - 2017-09-21
+### Added
+- Support for STM32L496VG MCU
+- Multiple build configurations for each supported microcontroller
+- Change between different builds with a single click
+### Changed
+- Updated FatFs to R0.12c
+- Updated Cortex-M CMSIS to 4.5
+- Updated STM32L4xx CMSIS to 1.4.0
+- Updated STM32L4xx HAL library to 1.8.0
+
+
+## [1.02](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.02) - 2017-08-11
+### Fixed
+- General improvements
+
+
+## [1.01](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.01) - 2017-07-25
+### Added
+- Option for clearing reset flags after startup
+### Fixed
+- Bootloader sequence graph
+- Readme updates
+- General improvements
+
+
+## [1.00](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.00) - 2017-05-21
+### Added
+Initial release
diff --git a/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h b/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h
@@ -862,12 +862,10 @@ typedef struct
   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */
   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
-  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
 } SPI_TypeDef;
 
 

diff --git a/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h b/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h
@@ -505,9 +505,9 @@ typedef struct
   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+  uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
 } DMA2D_TypeDef;
 
 /**
@@ -934,12 +934,10 @@ typedef struct
   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */
   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
-  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
 } SPI_TypeDef;
 
 
@@ -7777,7 +7775,6 @@ typedef struct
 #define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
 #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
 
-
 /********************  Bit definition for DMA2D_FGCLUT register  **************/
 
 /********************  Bit definition for DMA2D_BGCLUT register  **************/

diff --git a/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h b/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h
@@ -118,7 +118,7 @@
   */
 #define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
 #define __STM32L4_CMSIS_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
-#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
 #define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\

diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -431,12 +431,12 @@
 #define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
 #define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
 
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
 #define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
 #define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
 #define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
 #define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
 
 #if defined(STM32L1)
  #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
@@ -2119,6 +2119,21 @@
 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@@ -2787,7 +2802,9 @@
 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
 
-#if defined(STM32WB) || defined(STM32G0)
+#if defined(STM32L4)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0)
 #else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
 #endif
@@ -3038,6 +3055,16 @@
 #define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
 #endif
 
+#if defined(STM32H7)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#endif
 /**
   * @}
   */
@@ -3252,6 +3279,17 @@
   * @}
   */
 
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
 
 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
   * @{