CAN-bus Controller with AXI4-lite Interface

README structure:
Overview
Publications
Design Information
How-to-use
Disclamer
Contact Information

Overview

This project provides information and resources, in terms of hardware (synthesizable HDL code), software (C code) and documentation that enable the evaluation and testing of CAN-bus controllers operation and communication. Development boards equipped with FPGA and/or micro-controller and/or processor, which provides communicataion links between them, are suitable for porting this project. The provided sources have been tested over development boards equipped 32-bit ARM processors/micro-controllers, i.e., Zedboard (Xilinx Zynq-7000 + Cortex-A9) and SEcube (Lattice MachXO2 + Cortex-M4).

This work was partially funded by TAPPS Horizon2020 framework EU-funded project, ISCA-lab, colleagues and me, in order to fulfill project's and lab's goals. Demo videos related to TAPPS, with additional H/W and S/W extensions based on the requirements, can be found at ISCA-lab's Youtube channel.

Former and current colleages participated in the creation of the integrated system shown in videos (TAPPS demo videos):

• Bakoyiannis Dimitrios - [email protected]
• Deligiannis Ioannis - [email protected]
• Karadimitriou Nikolaos - [email protected]

Publications

Hardware-assisted Security in Electronic Control Units, Secure Automotive Communications by Utilizing One-Time-Programmable Network-on-Chip and Firewalls, G. Kornaros, O. Tomoutzoglou and M. Coppola, Sept./Oct. 2018, IEEE micro

Secure Over-the-air Firmware Updating for Automotive Electronic Control Units, *D. Mbakoyiannis, O. Tomoutzoglou and G. Kornaros, Apr. 2019, ACM SAC '19

A preprint of the first publication can be found at ISCA-lab's site.

Design Information

Hardware

The following, already implemented, cores have been used in order to achieve this project's goals:

• CAN Protocol Controller, authored by Igor Mohor ([email protected])
• Simple AXI4-Lite bridges for IPbus and Wishbone, authored by Wojciech M. Zabolotny ([email protected])

Contribution

• Patch files for the CAN controller that enables 8-bit addressing over a 32-bit addressable environment, provide access to extra added or already implemented registers, enriching interaction with the CAN controller; prevent faulty interrupt generation under certain circumstances etc. More information about the modifications made can be found in the header of the patched verilog sources
• Patch file for the AXI lite to WishBone adapter, to properly communicate with CAN controller's WishBone IF.
• A top module that wraps CAN controller and axi4-lite to wishbone adapter (axi_can.v)
• Test-bench sources (axi_can_tb.v)

Testbench info

• T = 10ns
• Two CAN controllers instances
  1. Operating in 2B (extended) mode with extended CAN frame format enabled
  2. Baud rate: 1000 kbps
  3. Filter (drop) all the CAN frames with header ID[28] equal to zero
  4. Single filtering
  5. Interrupt mode activated only for receiving CAN frames (active high)

During the test-bench two CAN controllers are instantiated; the first instance is ordered to send two CAN frames, where the first one's header MSB is '0', while the other one's is '1'; consecutively it is ordered to the second instance to read a CAN frame (IRQ mode). Although the second instance acknowledges both the frames (physical-layer), only one of the frames is forwarded to upper-levels (i.e., two frames, one RX interrupt), as the one with header's MSB equal to '0' is dropped by the filter's rules.

Expected waveform (only CAN bus & IRQs)

BAUD rate formula

$$ Baud\ Rate=\frac{1}{(BPR*clk\_period)*(1+TSEG1+TSEG2))} $$

NOTE 0

BRP (Baud Rate Prescaler), TSEG1 (Time SEGment), TSEG2 and SJW (Synchronization Jump Width)are the final values that CAN controller's Bit Time Logic uses, not the ones set through the API. The following list gives the mapping from the API given to the actual value that HW perceives:

$$ \begin{aligned} BRP &\mapsto 2*(BRP+1) \\ TSEG1 &\mapsto TSEG1+1 \\ TSEG2 &\mapsto TSEG2+1 \\ SJW &\mapsto SJW+1 \end{aligned} $$

NOTE 1

The proper constraints should applied for on TX and RX pins based on the CAN transceiver and the development board's characteristics, in terms of voltage, ampere, hysteresis, slew rates etc.

Design Abstract Diagram

     .-----------------------------------.
     |        Proccessing System         |
     |-----------------------------------|
     |   .---------------------------.   |
     |   |         Soft/Hard         |   |
     |   | Processor/Microcontroller |   |
     |   |---------------------------|   |
     |   |        Application        |   |
     |   '---------------------------'   |
     |                 |           ^     |
     '------------AXI4 |-----------|-----'
                       |           |
                       v           |
              .----------------.   | IRQ (optional)
              | CAN controller |---'
              '----------------'
                    |    ^
                    |    |
                    |    |
                    v    |
                  TX      RX

Software

The provided, under the sw/ folder, software gives the ability to a programmer to communicate with the CAN controller, i.e., initialization, setup, transmit(TX) and receive(RX) CAN frames etc., alongside a usage example contained in main.c

NOTE 2

Some of the functionality that the example code provides, i.e. CAN-2A/CAN-2B, POLL/INTERRUPT modes, can be selected at compile time; this can be achieved either by modifying ISCA_CAN_CFG.h or by passing to the compiler the appropriate options, e.g., gcc ... -DCAN_MODE=1. There follows all the available options.

$$ \begin{aligned} CAN\_MODE &\in {0,1},\ where\ 0\mapsto\ basic,\ 1\mapsto extended \\ APPRISE\_MODE &\in {0,1},\ where\ 0\mapsto\ Polling\ Mode,\ 1\mapsto\ Interrupt\ Mode \end{aligned} $$

For more detailed information about the provided software, file dependencies etc. you are encouraged to modify to your needs or taste and compile the provided Doxygen file and gain access to the provided software's documentation (installation of Doxygen is required. Tested over version 1.8.13). A pre-compiled version based on the Doxygen file HTML output exists zipped under drax/doc/SW/; ISCA_CAN_CFG.h definitions during compilation were the same as the current ones. Extract drax/doc/SW/html.zip and open html/index.html with your web browser; guide yourself through the code documentation.

NOTE 3

If it happens to have problem with the relative paths defined in Doxyfile, please consider updating them manually.

Doxygen generated code documentation sample output:

How-to-use

Build Hardware

Follow the next steps in order to produce a functional HW design:

• Clone this repository
• Download the sources for the CAN Protocol Controller project
• Copy all files from can/trunk/rtl/verilog/ to hw_srcs/rtl/ folder
• Copy all files from can/trunk/bench/verilog/, except can_testbench.v, to hw_srcs/bench/ folder
• Download the sources for the Simple AXI4-Lite bridges for IPbus and Wishbone project
• Copy ax4lbr/trunk/rtl/axil2wb to the hw_srcs/rtl/ folder
• Apply all the patch files found under hw_patches/ folder
  • Example: patch hw_srcs/rtl/axil2wb.vhd < hw_patches/axil2wb.patch

NOTE 4

All patch files were created using GNU diffutils' version 3.5 diff command.

After finishing the steps above you may use your EDA tool (synthesizer should support mixed VHDL-Verilog), in order to produce the appropriate programming file for your device, by importing all the files from hw_srcs/rtl/ and hw_srcs/bench/ folder. The following list shows the RTL and bench sources in the expected hierarchical order:

.
├──  can_testbench_defines.v (simulation)
├──  can_defines.v
└── axi_can_tb.v (simulation)
    └──axi_can.v
       ├── axil2wb.vhd
       └── can_top.v
           ├── can_registers.v
           │   ├── can_register_asyn_syn.v
           │   ├── can_register_asyn.v
           │   └── can_register.v
           ├── can_btl.v
           └── can_bsp.v
               ├── can_crc.v
               ├── can_acf.v
               ├── can_fifo.v
               └── can_ibo.v

Follow your EDA tool work flow to properly connect, synthesize and implement the design based on the selected development board; program the FPGA.

Build Software

Use your IDE or manually compile the code provided under sw/, after taking into consideration the appropriate code modification you should make in order to port the code according to your development board specifications; consulting to SW documentation might be necessary , by opening drax/doc/SW/html/index.html with a web browser.

Disclaimer

The CAN protocol is developed by Robert Bosch GmbH and protected by patents. Anybody who wants to implement this CAN IP core on silicon has to obtain a CAN protocol license from Bosch.

Contact Information

Tomoutzoglou Othon: [email protected], [email protected]