Bring out pcie_user_clk on SMA connectors on VCU108 and VCU118

Signed-off-by: Alex Forencich <[email protected]>
alexforencich · Dec 13, 2023 · 917a984 · 917a984
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commit 917a984
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diff --git a/example/VCU108/fpga/fpga.xdc b/example/VCU108/fpga/fpga.xdc
@@ -28,6 +28,11 @@ set_property CONFIG_MODE BPI16                         [current_design]
 #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
 #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
 
+# User SMA clock J34/J35
+set_property -dict {LOC AR14 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
+set_property -dict {LOC AT14 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
+#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
+
 # LEDs
 set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
 set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]

diff --git a/example/VCU108/fpga/rtl/fpga.v b/example/VCU108/fpga/rtl/fpga.v
@@ -32,6 +32,11 @@ THE SOFTWARE.
  * FPGA top-level module
  */
 module fpga (
+    /*
+     * Clock and reset
+     */
+    output wire       user_sma_clk_p,
+    output wire       user_sma_clk_n,
     /*
      * GPIO
      */
@@ -78,6 +83,14 @@ parameter BAR4_APERTURE = 16;
 wire pcie_user_clk;
 wire pcie_user_reset;
 
+// forward PCIe user clock out SMA connectors
+OBUFDS
+user_sma_clk_obufds_inst (
+    .I(pcie_user_clk),
+    .O(user_sma_clk_p),
+    .OB(user_sma_clk_n)
+);
+
 // GPIO
 wire btnu_int;
 wire btnl_int;

diff --git a/example/VCU118/fpga/fpga.xdc b/example/VCU118/fpga/fpga.xdc
@@ -34,6 +34,11 @@ set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
 #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
 
+# User SMA clock J34/J35
+set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
+set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
+#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
+
 # LEDs
 set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
 set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]

diff --git a/example/VCU118/fpga/rtl/fpga.v b/example/VCU118/fpga/rtl/fpga.v
@@ -32,6 +32,12 @@ THE SOFTWARE.
  * FPGA top-level module
  */
 module fpga (
+    /*
+     * Clock and reset
+     */
+    output wire        user_sma_clk_p,
+    output wire        user_sma_clk_n,
+
     /*
      * GPIO
      */
@@ -78,6 +84,14 @@ parameter BAR4_APERTURE = 16;
 wire pcie_user_clk;
 wire pcie_user_reset;
 
+// forward PCIe user clock out SMA connectors
+OBUFDS
+user_sma_clk_obufds_inst (
+    .I(pcie_user_clk),
+    .O(user_sma_clk_p),
+    .OB(user_sma_clk_n)
+);
+
 // GPIO
 wire btnu_int;
 wire btnl_int;