modify dram setting for DL

board/freescale/mx6q_savage/flash_header.S

@@ -210,22 +210,22 @@ MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x48c, 0x00000030)
 MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
 
 # write leveling
-MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F0001 /*0x001F001F*/)
 MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
-MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
-MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F0001 /*0x001F001F*/)
+MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x0001001F /*0x001F001F*/)
 # DQS gating, read delay, write delay calibration values
 # based on calibration compare of 0x00ffff00
-MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42480248)
-MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x0211020B)
-MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x417F0211)
-MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x015D0166)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x421E020D /*0x42480248*/)
+MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x0201017B /*0x0211020B*/)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x41750200 /*0x417F0211*/)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x016B017D /*0x015D0166*/)
 
-MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4B4C504D)
-MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x494C4F48)
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x44414A44 /*0x4B4C504D*/)
+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x45484846 /*0x494C4F48*/)
 
-MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F2E31)
-MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x2B35382B)
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x403F3137 /*0x3F3F2E31*/)
+MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x3236363F /*0x2B35382B*/)
 
 MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
 MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)