ad738x: ALERT/SDOB-SDOD Output (#1352)

Signed-off-by: Ioan-daniel Pop <[email protected]>
analogdevicesinc · Jul 8, 2024 · 1652d0b · 1652d0b
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diff --git a/docs/projects/ad738x_fmc/ad738x_spi_engine_hdl.svg b/docs/projects/ad738x_fmc/ad738x_spi_engine_hdl.svg
diff --git a/docs/projects/ad738x_fmc/index.rst b/docs/projects/ad738x_fmc/index.rst
@@ -8,7 +8,7 @@ Overview
 
 The :adi:`AD7380`/ :adi:`AD7381` are a 16-bit and 14-bit pin-compatible family
 of dual simultaneous sampling, high speed, low power, successive approximation
-register (SAR) analog-to-digital converters (ADCs) that operate from a 3.3 V 
+register (SAR) analog-to-digital converters (ADCs) that operate from a 3.3 V
 power supply and feature throughput rates up to 4 MSPS.The analog input type is
 differential for the :adi:`AD7380`, :adi:`AD7381`, :adi:`AD4680`, :adi:`AD4681`,
 :adi:`AD7380-4`, :adi:`AD7389-4`, :adi:`AD7381-4` can accepts a wide common-mode
@@ -19,17 +19,17 @@ pseudo-differential input while the :adi:`AD7386`, :adi:`AD7387`, :adi:`AD7388`,
 :adi:`AD4684` and :adi:`AD4685` have single-ended input. The AD7380 family has
 optional integrated on-chip oversampling blocks to improve dynamic range and
 reduce noise at lower bandwidths. An internal 2.5 V reference is included.
-Alternatively, an external reference up to 3.3 V can be used. 
+Alternatively, an external reference up to 3.3 V can be used.
 
 The conversion process and data acquisition use standard control inputs allowing
 for easy interfacing to microprocessors or DSPs. It is compatible with 1.8 V,
 2.5 V, and 3.3 V interfaces, using a separate logic supply.
 
-The dual :adi:`AD7380`, :adi:`AD7381`, :adi:`AD4680`, :adi:`AD4681`, 
+The dual :adi:`AD7380`, :adi:`AD7381`, :adi:`AD4680`, :adi:`AD4681`,
 :adi:`AD7383`, :adi:`AD7384`, :adi:`AD4682`, :adi:`AD4683`, :adi:`AD7386`,
 :adi:`AD7387`, :adi:`AD7388`, :adi:`AD4684` and :adi:`AD4685` family are
 available in a 16-lead 3mm x 3mm LFCSP package while the quad generics
-:adi:`AD7380-4`, :adi:`AD7389-4`, and :adi:`AD7381-4` are available in 
+:adi:`AD7380-4`, :adi:`AD7389-4`, and :adi:`AD7381-4` are available in
 4mmx4mm LFCSP package. Both the duals and quad generic operate in specified
 from -40°C to +125°C temperature range.
 
@@ -55,12 +55,18 @@ Supported devices
 -------------------------------------------------------------------------------
 
 -  :adi:`AD7380`
+-  :adi:`AD7380-4`
 -  :adi:`AD7381`
+-  :adi:`AD7381-4`
 -  :adi:`AD7383`
+-  :adi:`AD7383-4`
 -  :adi:`AD7384`
+-  :adi:`AD7384-4`
 -  :adi:`AD7386`
 -  :adi:`AD7387`
 -  :adi:`AD7388`
+-  :adi:`AD7388-4`
+-  :adi:`AD7389-4`
 -  :adi:`AD4680`
 -  :adi:`AD4681`
 -  :adi:`AD4682`
@@ -86,6 +92,35 @@ The data path and clock domains are depicted in the below diagram:
    :align: center
    :alt: AD738X_FMC block diagram
 
+Configuration modes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ALERT_SPI_N configuration parameter defines if a known pin will operate as a
+serial data output pin or alert indication pin. By default it is set to 0.
+Depending on the required pin functionality, some hardware modifications need to
+be done on the board and/or ``make`` command:
+
+In case of the **Serial Data Output Pin** functionality:
+
+.. code-block::
+
+   make ALERT_SPI_N=0
+
+In case of the **Alert Indication Output Pin** functionality:
+
+.. code-block::
+
+   make ALERT_SPI_N=1
+
+The NUM_OF_SDI configuration parameter defines the number of SDI lines used:
+-  Options: 1, 2, 4.
+By default is set to 1.
+
+For the ALERT functionality, the following parameters will be used in make
+command: ALERT_SPI_N.
+For the serial data output functionality, the following parameters will be
+used in make command: ALERT_SPI_N, NUM_OF_SDI.
+
 Jumper setup
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -98,17 +133,17 @@ LK3                1                 Use 12 V power supply from FMC
 LK4                3                 Use internal +3V3 from U3 for VREF
 LK5                3                 Use internal 2.3 V from U6 for VLOGIC
 JP1                1 (SMD RES)       Connect external SubMiniature Version B
-                                     (SMB) Connector J1 to the A1 buffer 
+                                     (SMB) Connector J1 to the A1 buffer
                                      amplifier
 JP2                1 (SMD RES)       Connect internal signal from A2 to ADC U10
-                                     input AINA- 
+                                     input AINA-
 JP3                1 (SMD RES)       Connect internal signal from A2 to ADC U10
-                                     input AINA+ 
+                                     input AINA+
 JP4                3 (SMD RES)       The REFIO pin is driven with the external
-                                     on board reference     
-JP5                1 (SMD RES)       Use internal +3V3 from U2 for VCC. 
+                                     on board reference
+JP5                1 (SMD RES)       Use internal +3V3 from U2 for VCC.
 JP6                1 (SMD RES)       Connect external SMB Connector J2 to the
-                                     A1 buffer amplifier        
+                                     A1 buffer amplifier
 ================== ================= ==========================================
 
 CPU/Memory interconnects addresses
@@ -165,6 +200,42 @@ SPI connections
      - ad738x
      - 0
 
+GPIOs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Software GPIO number is calculated as follows:
+
+-  Zynq-7000: if PS7 is used, then the offset is 54
+
+.. list-table::
+   :widths: 25 25 25 25 25 25
+   :header-rows: 2
+
+   * - GPIO signal
+     - Direction
+     - HDL GPIO EMIO
+     - Software GPIO
+     - Assigned value
+     - Assigned value
+   * -
+     - (from FPGA view)
+     -
+     - Zynq-7000
+     - ALERT_SPI_N=1
+     - ALERT_SPI_N=0
+   * - gpio[33]
+     - OUT
+     - 33
+     - 87
+     - sdid
+     - 0
+   * - gpio[32]
+     - OUT
+     - 32
+     - 86
+     - sdib
+     - 0
+
 Interrupts
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -193,7 +264,18 @@ the HDL repository, and then build the project as follows:
    :linenos:
 
    user@analog:~$ cd hdl/projects/ad738x_fmc/zed
-   user@analog:~/hdl/projects/ad738x_fmc/zed$ make
+   user@analog:~/hdl/projects/ad738x_fmc/zed$ make ALERT_SPI_N=0 NUM_OF_SDI=4
+
+The result of the build, if parameters were used, will be in a folder named
+by the configuration used:
+
+if the following command was run
+
+``make ALERT_SPI_N=0 NUM_OF_SDI=4``
+
+then the folder name will be:
+
+``ALERTSPIN0_NUMOFSDI4``
 
 A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
 
@@ -206,12 +288,18 @@ Hardware related
 -  Product datasheets:
 
    -  :adi:`AD7380`
+   -  :adi:`AD7380-4`
    -  :adi:`AD7381`
+   -  :adi:`AD7381-4`
    -  :adi:`AD7383`
+   -  :adi:`AD7383-4`
    -  :adi:`AD7384`
+   -  :adi:`AD7384-4`
    -  :adi:`AD7386`
    -  :adi:`AD7387`
    -  :adi:`AD7388`
+   -  :adi:`AD7388-4`
+   -  :adi:`AD7389-4`
    -  :adi:`AD4680`
    -  :adi:`AD4681`
    -  :adi:`AD4682`
@@ -264,7 +352,7 @@ HDL related
      - :ref:`here <spi_engine interconnect>`
    * - SPI_ENGINE_OFFLOAD
      - :git-hdl:`library/spi_engine/spi_engine_offload <library/spi_engine/spi_engine_offload>`
-     - :ref:`here <spi_engine offload>`  
+     - :ref:`here <spi_engine offload>`
    * - SYSID_ROM
      - :git-hdl:`library/sysid_rom <library/sysid_rom>`
      - :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`

diff --git a/projects/ad738x_fmc/Readme.md b/projects/ad738x_fmc/Readme.md
@@ -3,10 +3,38 @@
 Here are some pointers to help you:
   * [Board Product Page](https://www.analog.com/eval-ad738xfmcz)
   * Parts : [AD7380, 4MSPS Dual Simultaneous Sampling, 16-BIT SAR ADC, Differential Input](https://www.analog.com/ad7380)
+  * Parts : [AD7380-4, 4MSPS Quad, External Reference Simultaneous Sampling, 16-Bit, SAR ADC, Differential Input](https://www.analog.com/ad7380-4)
   * Parts : [AD7381, 4MSPS Dual Simultaneous Sampling, 14-BIT SAR ADC, Differential Input](https://www.analog.com/ad7381)
+  * Parts : [AD7381-4, 4MSPS Quad, 14-Bit, Simultaneous Sampling, SAR ADC, Differential Input](https://www.analog.com/ad7381-4)
+  * Parts : [AD7383-4, 4MSPS Quad, Simultaneous Sampling, 16-Bit, SAR ADC, Pseudo Differential Input](https://www.analog.com/ad7383-4)
+  * Parts : [AD7384-4, 4MSPS Quad, Simultaneous Sampling, 14-Bit, SAR ADC, Pseudo Differential Input](https://www.analog.com/ad7384-4)
   * Parts : [AD7386, 4-Channel, 4 MSPS, 16-Bit Dual Simultaneous Sampling SAR ADC](https://www.analog.com/ad7386)
   * Parts : [AD7387, 4-Channel, 4 MSPS, 14-Bit, Dual, Simultaneous Sampling SAR ADC](https://www.analog.com/ad7387)
   * Parts : [AD7388, 4-Channel, 4 MSPS, 12-Bit, Dual, Simultaneous Sampling SAR ADCs](https://www.analog.com/ad7388)
+  * Parts : [AD7389-4, 4MSPS Quad, Internal Reference Simultaneous Sampling, 16-Bit SAR ADC, Differential Input](https://www.analog.com/ad7389-4)
   * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad738x
   * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad738x
   * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad738x
+# Building, Generating Bit Files
+
+How to use over-writable parameters from the environment:
+```
+hdl/projects/ad738x_fmc/zed> make ALERT_SPI_N=0 NUM_OF_SDI=4
+```
+
+SDOB-SDOD/ALERT pin can operate as a serial data output pin or alert indication output depending on its value:
+* 0 - SDOB-SDOD
+* 1 - ALERT
+
+NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4
+
+For the ALERT functionality, the following parameters will be used in make command: ALERT_SPI_N
+For the serial data output functionality, the following parameters will be used in make command: ALERT_SPI_N, NUM_OF_SDI
+
+**Example:**
+```
+make ALERT_SPI_N=0 NUM_OF_SDI=1
+make ALERT_SPI_N=0 NUM_OF_SDI=2
+make ALERT_SPI_N=0 NUM_OF_SDI=4
+make ALERT_SPI_N=1
+```
diff --git a/projects/ad738x_fmc/common/ad738x_bd.tcl b/projects/ad738x_fmc/common/ad738x_bd.tcl
@@ -3,14 +3,22 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# system level parameter
+
+set ALERT_SPI_N $ad_project_params(ALERT_SPI_N)
+set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
+
+puts "build parameter: ALERT_SPI_N: $ALERT_SPI_N"
+puts "build parameter: NUM_OF_SDI: $NUM_OF_SDI"
+
 create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad738x_spi
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    16
+set data_width    32
 set async_spi_clk 1
 set num_cs        1
-set num_sdi       2
+set num_sdi       [expr {$ALERT_SPI_N ? 1 : $NUM_OF_SDI}]
 set num_sdo       1
 set sdi_delay     1
 set echo_sclk     0
@@ -32,7 +40,7 @@ ad_ip_parameter axi_ad738x_dma CONFIG.SYNC_TRANSFER_START 0
 ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_SRC 0
 ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_DEST 1
 ad_ip_parameter axi_ad738x_dma CONFIG.DMA_2D_TRANSFER 0
-ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_SRC 32
+ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $num_sdi]
 ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
 
 ad_ip_instance axi_clkgen spi_clkgen

diff --git a/projects/ad738x_fmc/common/ad738x_fmc.txt b/projects/ad738x_fmc/common/ad738x_fmc.txt
@@ -4,6 +4,8 @@ FMC_pin   FMC_port               Schematic_name     System_top_name     IOSTANDA
 
 D8        FMC_LA01_CC_P          SDOA               spi_sdia            LVCMOS25    #N/A
 D9        FMC_LA01_CC_N          SDOB               spi_sdib            LVCMOS25    #N/A
+H8        FMC_LA02_N             SDOC               spi_sdic            LVCMOS25    #N/A
+G9        FMC_LA03_P             SDOD               spi_sdid            LVCMOS25    #N/A
 G6        FMC_LA00_CC_P          SCLK               spi_sclk            LVCMOS25    #N/A
 G7        FMC_LA00_CC_N          CS                 spi_cs              LVCMOS25    #N/A
 H7        FMC_LA02_P             SDI                spi_sdo             LVCMOS25    #N/A