common: vcu118 vcu128: Update interconnect name

With the rework of ad_cpu_interconnect to allow other PS AXI manager ports, the interconnect IP name now reflects the AXI manager port name. Rename axi_cpu_interconnect in projects to match the PS AXI manager port name. Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Sep 4, 2024 · 4971995 · 4971995
1 parent 398b4b4
commit 4971995
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diff --git a/projects/common/vcu118/vcu118_system_bd.tcl b/projects/common/vcu118/vcu118_system_bd.tcl
@@ -286,8 +286,8 @@ ad_cpu_interconnect 0x44A70000 axi_spi
 ad_cpu_interconnect 0x41400000 sys_mb_debug
 
 ## Peripheral Data Interface runs at the new sys_mb_clk frequency
-ad_ip_parameter axi_cpu_interconnect CONFIG.NUM_CLKS 2
-ad_connect sys_mb_clk axi_cpu_interconnect/aclk1
+ad_ip_parameter axi_dp_interconnect CONFIG.NUM_CLKS 2
+ad_connect sys_mb_clk axi_dp_interconnect/aclk1
 
 # interconnect - memory
 

diff --git a/projects/common/vcu128/vcu128_system_bd.tcl b/projects/common/vcu128/vcu128_system_bd.tcl
@@ -326,11 +326,11 @@ ad_cpu_interconnect 0x45100000 axi_ddr_cntrl C0_DDR4_S_AXI_CTRL
 
 ### Workaround for DDR controller with control interface
 ### DDR contoller control interface runs at UI clock not CPU clock
-set_property -dict [list CONFIG.NUM_CLKS {3}] [get_bd_cells axi_cpu_interconnect]
-ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk  axi_cpu_interconnect/aclk1
+set_property -dict [list CONFIG.NUM_CLKS {3}] [get_bd_cells axi_dp_interconnect]
+ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk  axi_dp_interconnect/aclk1
 
 ### Peripheral Data Interface runs at the sys_mb_clk frequency
-ad_connect sys_mb_clk axi_cpu_interconnect/aclk2
+ad_connect sys_mb_clk axi_dp_interconnect/aclk2
 
 # interconnect - memory