Update cn0363 spi engine

I replaced the SPI Engine connections in the cn0363_bd.tcl with the spi_engine_create procedure found in the spi_engine.tcl script. Through these changes, a more generic instantiation for the spi_engine can be achieved. I updated the system_constr.xdc file and created the cn0363_pmod.txt file. Signed-off-by: Ioan-daniel Pop <[email protected]>
analogdevicesinc · Sep 28, 2023 · 4e13af5 · 4e13af5
1 parent 9f82455
commit 4e13af5
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Showing 4 changed files with 50 additions and 79 deletions.
diff --git a/projects/cn0363/common/cn0363_bd.tcl b/projects/cn0363/common/cn0363_bd.tcl
@@ -3,6 +3,10 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
+
 proc load_fir_filter_vector {filter_file} {
 	set fp [open $filter_file r]
 	set data [split [read $fp] "\n"]
@@ -42,64 +46,32 @@ ad_ip_parameter axi_dma CONFIG.DMA_DATA_WIDTH_DEST 64
 ad_ip_parameter axi_dma CONFIG.DMA_AXI_PROTOCOL_DEST 1
 
 # Create SPI engine controller with offload
-create_bd_cell -type hier spi
-current_bd_instance /spi
 
-	create_bd_pin -dir I -type clk clk
-	create_bd_pin -dir I -type rst resetn
-	create_bd_pin -dir O conv_done
-	create_bd_pin -dir O irq
-	create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
-	create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
-
-  ad_ip_instance spi_engine_execution execution
-  ad_ip_instance axi_spi_engine axi
-  ad_ip_instance spi_engine_offload offload
-  ad_ip_instance spi_engine_interconnect interconnect
-  ad_ip_instance util_sigma_delta_spi util_sigma_delta_spi
-
-  ad_ip_parameter execution CONFIG.NUM_OF_CS 2
-  ad_ip_parameter util_sigma_delta_spi CONFIG.NUM_OF_CS 2
-  ad_ip_parameter interconnect CONFIG.NUM_OF_SDI 2
-  ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
-
-	ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
-	ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
-	ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
-	ad_connect interconnect/m_ctrl execution/ctrl
-	ad_connect offload/offload_sdi M_AXIS_SAMPLE
-
-	ad_connect util_sigma_delta_spi/data_ready offload/trigger
-	ad_connect util_sigma_delta_spi/data_ready conv_done
-
-	ad_connect execution/active util_sigma_delta_spi/spi_active
-	ad_connect execution/spi util_sigma_delta_spi/s_spi
-	ad_connect util_sigma_delta_spi/m_spi m_spi
+set data_width    8
+set async_spi_clk 0
+set num_cs        2
+set num_sdi       1
+set num_sdo       1
+set sdi_delay     1
+set echo_sclk     0
 
-	connect_bd_net \
-		[get_bd_pins clk] \
-		[get_bd_pins offload/spi_clk] \
-		[get_bd_pins offload/ctrl_clk] \
-		[get_bd_pins execution/clk] \
-		[get_bd_pins axi/s_axi_aclk] \
-		[get_bd_pins axi/spi_clk] \
-		[get_bd_pins interconnect/clk] \
-		[get_bd_pins util_sigma_delta_spi/clk]
+set hier_spi_engine spi_cn0363
 
-	connect_bd_net \
-		[get_bd_pins axi/spi_resetn] \
-		[get_bd_pins offload/spi_resetn] \
-		[get_bd_pins execution/resetn] \
-		[get_bd_pins interconnect/resetn] \
-		[get_bd_pins util_sigma_delta_spi/resetn]
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
-	connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn]
-	ad_connect irq axi/irq
+ad_connect $sys_cpu_clk $hier_spi_engine/clk
+ad_connect sys_cpu_resetn $hier_spi_engine/resetn
 
-current_bd_instance /
+ad_ip_instance util_sigma_delta_spi util_sigma_delta_spi
+ad_ip_parameter util_sigma_delta_spi CONFIG.NUM_OF_CS $num_cs
 
-create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
-ad_connect spi/m_spi spi
+ad_connect $hier_spi_engine/clk util_sigma_delta_spi/clk
+ad_connect util_sigma_delta_spi/resetn $hier_spi_engine/resetn
+
+ad_connect $hier_spi_engine/m_spi util_sigma_delta_spi/s_spi
+ad_connect util_sigma_delta_spi/data_ready $hier_spi_engine/trigger
+ad_connect $hier_spi_engine/${hier_spi_engine}_execution/active util_sigma_delta_spi/spi_active
+ad_connect util_sigma_delta_spi/m_spi spi
 
 ad_ip_instance c_counter_binary phase_gen
 ad_ip_instance xlslice phase_slice
@@ -248,9 +220,9 @@ current_bd_instance /processing
 
 current_bd_instance /
 
-ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE
-ad_connect /spi/conv_done /processing/conv_done
+ad_connect /processing/S_AXIS_SAMPLE $hier_spi_engine/M_AXIS_SAMPLE
 ad_connect /phase_gen/Q /processing/phase
+ad_connect util_sigma_delta_spi/data_ready /processing/conv_done
 
 ad_ip_instance axi_generic_adc axi_adc
 ad_ip_parameter axi_adc	CONFIG.NUM_OF_CHANNELS 14
@@ -259,26 +231,24 @@ ad_connect processing/overflow axi_adc/adc_dovf
 ad_connect axi_adc/adc_enable processing/channel_enable
 
 connect_bd_net -net $sys_cpu_clk \
-	[get_bd_pins /spi/clk] \
 	[get_bd_pins /processing/clk] \
 	[get_bd_pins /axi_dma/m_dest_axi_aclk] \
 	[get_bd_pins /axi_dma/fifo_wr_clk] \
 	[get_bd_pins /phase_gen/CLK] \
 	[get_bd_pins /axi_adc/adc_clk]
 
 connect_bd_net -net $sys_cpu_resetn \
-	[get_bd_pins /spi/resetn] \
 	[get_bd_pins /processing/resetn] \
 	[get_bd_pins /axi_dma/m_dest_axi_aresetn]
 
 ad_connect /processing/dma_wr /axi_dma/fifo_wr
 
 ad_cpu_interconnect 0x43c00000 /axi_adc
-ad_cpu_interconnect 0x44a00000 /spi/axi
+ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
 ad_cpu_interconnect 0x44a30000 /axi_dma
 
 ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq
-ad_cpu_interrupt "ps-12" "mb-12" /spi/irq
+ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
 
 ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect $sys_cpu_clk axi_dma/m_dest_axi
+ad_mem_hp2_interconnect $sys_cpu_clk axi_dma/m_dest_axi
diff --git a/projects/cn0363/common/cn0363_pmod.txt b/projects/cn0363/common/cn0363_pmod.txt
@@ -0,0 +1,12 @@
+# cn0363
+
+Pin            Port               Schematic_name     System_top_name        IOSTANDARD  Termination
+
+PMOD [2]       PMOD JA1           GAIN0              gain0_o                LVCMOS33    #N/A
+PMOD [4]       PMOD JA2           GAIN1              gain1_o                LVCMOS33    #N/A
+PMOD [8]       PMOD JA4           EXT_LED_CLK        led_clk_o              LVCMOS33    #N/A
+PMOD [6]       PMOD JA3           DA_CSn             spi_cs[1]              LVCMOS33    #N/A
+PMOD [1]       PMOD JA7           AD_CSn             spi_cs[0]              LVCMOS33    #N/A
+PMOD [3]       PMOD JA8           AD_DIN             spi_sdo                LVCMOS33    PULLTYPE PULLUP
+PMOD [5]       PMOD JA9           AD_DOUT            spi_sdi                LVCMOS33    PULLTYPE PULLUP
+PMOD [7]       PMOD JA10          AD_CLK             spi_sclk               LVCMOS33    #N/A
diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile
@@ -10,6 +10,7 @@ M_DEPS += ../common/cn0363_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
+M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
 LIB_DEPS += axi_clkgen

diff --git a/projects/cn0363/zed/system_constr.xdc b/projects/cn0363/zed/system_constr.xdc
@@ -5,23 +5,11 @@
 
 # PMOD JA
 
-set_property PACKAGE_PIN Y11 [get_ports gain0_o]
-set_property IOSTANDARD LVCMOS33 [get_ports gain0_o]
-set_property PACKAGE_PIN AA11 [get_ports gain1_o]
-set_property IOSTANDARD LVCMOS33 [get_ports gain1_o]
-set_property PACKAGE_PIN AA9 [get_ports led_clk_o]
-set_property IOSTANDARD LVCMOS33 [get_ports led_clk_o]
-set_property PACKAGE_PIN Y10 [get_ports {spi_cs[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[1]}]
-
-set_property PACKAGE_PIN AB11 [get_ports {spi_cs[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[0]}]
-set_property PACKAGE_PIN AB10 [get_ports spi_sdo]
-set_property IOSTANDARD LVCMOS33 [get_ports spi_sdo]
-set_property PULLUP true [get_ports spi_sdo]
-set_property PACKAGE_PIN AB9 [get_ports spi_sdi]
-set_property IOSTANDARD LVCMOS33 [get_ports spi_sdi]
-set_property PULLUP true [get_ports spi_sdi]
-set_property PACKAGE_PIN AA8 [get_ports spi_sclk]
-set_property IOSTANDARD LVCMOS33 [get_ports spi_sclk]
-
+set_property -dict {PACKAGE_PIN Y11  IOSTANDARD LVCMOS33} [get_ports gain0_o]                       ; ## PMOD [2] PMOD JA1  IO_L10P_T1
+set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports gain1_o]                       ; ## PMOD [4] PMOD JA2  IO_L8P_T1
+set_property -dict {PACKAGE_PIN AA9  IOSTANDARD LVCMOS33} [get_ports led_clk_o]                     ; ## PMOD [8] PMOD JA4  IO_L11P_T1_SRCC
+set_property -dict {PACKAGE_PIN Y10  IOSTANDARD LVCMOS33} [get_ports {spi_cs[1]}]                   ; ## PMOD [6] PMOD JA3  IO_L10N_T1
+set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS33} [get_ports {spi_cs[0]}]                   ; ## PMOD [1] PMOD JA7  IO_L8N_T1
+set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports spi_sdo]           ; ## PMOD [3] PMOD JA8  IO_L9P_T1_DQS
+set_property -dict {PACKAGE_PIN AB9  IOSTANDARD LVCMOS33 PULLUP true} [get_ports spi_sdi]           ; ## PMOD [5] PMOD JA9  IO_L9N_T1_DQS
+set_property -dict {PACKAGE_PIN AA8  IOSTANDARD LVCMOS33} [get_ports spi_sclk]                      ; ## PMOD [7] PMOD JA10 IO_L11N_T1_SRCC