axi_dmac: Implement generic transfer start sync

This commit adds a generic 'sync' port used for transfer start. The signal used for synchronization is assumed to be synchronous with the interface clock. On the receive AXI Streaming interface, the user can choose to receive the synchronization signal on TUSER instead of 'sync', which is the default setting, configurable through the AXIS_TUSER_SYNC synthesis parameter. Updated the library, docs and projects to include this change. Fixed issues in projects: connected unused sync signals to GND and fixed the timing violations in fmcomms8/a10soc. Signed-off-by: Ionut Podgoreanu <[email protected]>
analogdevicesinc · Jul 16, 2024 · 9ca41b7 · 9ca41b7
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diff --git a/docs/library/axi_dmac/index.rst b/docs/library/axi_dmac/index.rst
@@ -102,6 +102,8 @@ Configuration Parameters
      - Whether to insert an extra register slice on the source data path.
    * - AXI_SLICE_SRC
      - Whether to insert an extra register slice on the destination data path.
+   * - AXIS_TUSER_SYNC
+     - Transfer Start Synchronization on TUSER
    * - SYNC_TRANSFER_START
      - Enable the transfer start synchronization feature.
    * - CYCLIC
@@ -656,19 +658,32 @@ of the application.
 Transfer Start Synchronization
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-If the transfer start synchronization feature of the DMA controller is enabled
-the start of a transfer is synchronized to a flag in the data stream. This is
-primarily useful if the data stream does not have any back-pressure and one unit
+If the ``SYNC_TRANSFER_START`` HDL synthesis configuration parameter is set, the
+transfer start synchronization feature of the DMA controller is enabled. This
+means that the start of a transfer is synchronized to a flag in the data stream
+or a sync signal.
+
+This is useful if the data stream does not have any back-pressure and one unit
 of data spans multiple beats (e.g. packetized data). This ensures that the data
 is properly aligned to the beginning of the memory buffer.
 
-Data that is received before the synchronization flag is asserted will be
-ignored by the DMA controller.
+In addition, this feature allows the implementation of external timing
+synchronization for precisely timed buffers (For example, in combination with the
+:git-hdl:`Timing-Division Duplexing Controller <library/axi_tdd>`).
+
+On the transmit side, both the FIFO and AXI-Streaming interfaces use the ``sync``
+signal as the synchronization signal.
+
+On the receive side, for the FIFO write interface the ``sync`` signal represents
+the synchronization flag signal. For the AXI-Streaming interface the synchronization
+signal is carried in either ``s_axis_user[0]`` or ``sync``, depending on the
+value of ``S_AXIS_USER_SYNC`` synthesis configuration parameter. In both cases
+the synchronization signal is qualified by the same control signal as the data.
+
+.. note::
 
-For the FIFO write interface the ``fifo_wr_sync`` signal is the synchronization
-flag signal. For the AXI-Streaming interface the synchronization flag is carried
-in ``s_axis_user[0]``. In both cases the synchronization flag is qualified by
-the same control signal as the data.
+   The synchronization signal is assumed to be synchronous with the clock of the
+   interface which needs to be triggered by the transfer start synchronization.
 
 Cache Coherency
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

diff --git a/docs/regmap/adi_regmap_dmac.txt b/docs/regmap/adi_regmap_dmac.txt
@@ -9,7 +9,7 @@ ENDTITLE
 REG
 0x000
 VERSION
-Version of the peripheral. Follows semantic versioning. Current version 4.05.62.
+Version of the peripheral. Follows semantic versioning. Current version 4.05.63.
 ENDREG
 
 FIELD
@@ -25,7 +25,7 @@ RO
 ENDFIELD
 
 FIELD
-[7:0] 0x00000062
+[7:0] 0x00000063
 VERSION_PATCH
 RO
 ENDFIELD
@@ -368,7 +368,7 @@ X_LENGTH
 ENDREG
 
 FIELD
-[23:0] 2^log2(max(''DMA_DATA_WIDTH_SRC'', ''DMA_DATA_WIDTH_DEST'')/8)-1
+[31:0] 2^log2(max(''DMA_DATA_WIDTH_SRC'', ''DMA_DATA_WIDTH_DEST'')/8)-1
 X_LENGTH
 RW
 Number of bytes to transfer - 1.
@@ -383,7 +383,7 @@ Y_LENGTH
 ENDREG
 
 FIELD
-[23:0] 0x00000000
+[31:0] 0x00000000
 Y_LENGTH
 RW
 Number of rows to transfer - 1.
@@ -400,7 +400,7 @@ DEST_STRIDE
 ENDREG
 
 FIELD
-[23:0] 0x00000000
+[31:0] 0x00000000
 DEST_STRIDE
 RW
 The number of bytes between the start of one row and the next row for the
@@ -419,7 +419,7 @@ SRC_STRIDE
 ENDREG
 
 FIELD
-[23:0] 0x00000000
+[31:0] 0x00000000
 SRC_STRIDE
 RW
 The number of bytes between the start of one row and the next row for the source
@@ -551,7 +551,7 @@ TRANSFER_PROGRESS
 ENDREG
 
 FIELD
-[23:0] 0x000000
+[31:0] 0x00000000
 TRANSFER_PROGRESS
 RO
 This field presents the number of bytes transferred to the destination for the current transfer.

diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
@@ -52,6 +52,7 @@ module axi_dmac #(
   parameter ASYNC_CLK_DEST_SG = 1,
   parameter AXI_SLICE_DEST = 0,
   parameter AXI_SLICE_SRC = 0,
+  parameter AXIS_TUSER_SYNC = 1,
   parameter SYNC_TRANSFER_START = 0,
   parameter CYCLIC = 1,
   parameter DMA_AXI_PROTOCOL_DEST = 0,
@@ -102,6 +103,9 @@ module axi_dmac #(
   // Interrupt
   output irq,
 
+  // Transfer Start Sync Signal
+  input sync,
+
   // Master AXI interface
   input                                    m_dest_axi_aclk,
   input                                    m_dest_axi_aresetn,
@@ -273,10 +277,9 @@ module axi_dmac #(
   input                                    fifo_wr_en,
   input  [DMA_DATA_WIDTH_SRC-1:0]          fifo_wr_din,
   output                                   fifo_wr_overflow,
-  input                                    fifo_wr_sync,
   output                                   fifo_wr_xfer_req,
 
-  // Input FIFO interface
+  // Output FIFO interface
   input                                    fifo_rd_clk,
   input                                    fifo_rd_en,
   output                                   fifo_rd_valid,
@@ -533,6 +536,7 @@ module axi_dmac #(
     .ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG),
     .AXI_SLICE_DEST(AXI_SLICE_DEST),
     .AXI_SLICE_SRC(AXI_SLICE_SRC),
+    .AXIS_TUSER_SYNC(AXIS_TUSER_SYNC),
     .MAX_BYTES_PER_BURST(REAL_MAX_BYTES_PER_BURST),
     .FIFO_SIZE(FIFO_SIZE),
     .ID_WIDTH(ID_WIDTH),
@@ -561,6 +565,7 @@ module axi_dmac #(
     .req_dest_stride(up_dma_req_dest_stride),
     .req_src_stride(up_dma_req_src_stride),
     .req_sync_transfer_start(up_dma_req_sync_transfer_start),
+    .req_sync(sync),
     .req_last(up_dma_req_last),
 
     .req_eot(up_req_eot),
@@ -645,7 +650,6 @@ module axi_dmac #(
     .fifo_wr_en(fifo_wr_en),
     .fifo_wr_din(fifo_wr_din),
     .fifo_wr_overflow(fifo_wr_overflow),
-    .fifo_wr_sync(fifo_wr_sync),
     .fifo_wr_xfer_req(fifo_wr_xfer_req),
 
     .fifo_rd_clk(fifo_rd_clk),

diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl
@@ -166,24 +166,33 @@ foreach {suffix group} { \
   set_parameter_property AXI_SLICE_$suffix GROUP $group
 }
 
+add_parameter AXIS_TUSER_SYNC INTEGER 1
+set_parameter_property AXIS_TUSER_SYNC DISPLAY_NAME "TUSER Synchronization"
+set_parameter_property AXIS_TUSER_SYNC DESCRIPTION "Transfer Start Synchronization on TUSER"
+set_parameter_property AXIS_TUSER_SYNC DISPLAY_HINT boolean
+set_parameter_property AXIS_TUSER_SYNC HDL_PARAMETER true
+set_parameter_property AXIS_TUSER_SYNC GROUP "Source"
+
 # FIFO interface
 set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2
 
+add_display_item "Endpoint Configuration" "Scatter-Gather" "group"
+
 # Scatter-Gather interface
 add_parameter DMA_AXI_PROTOCOL_SG INTEGER 1
 set_parameter_property DMA_AXI_PROTOCOL_SG DISPLAY_NAME "AXI Protocol"
 set_parameter_property DMA_AXI_PROTOCOL_SG HDL_PARAMETER true
 set_parameter_property DMA_AXI_PROTOCOL_SG ALLOWED_RANGES { "0:AXI4" "1:AXI3" }
 set_parameter_property DMA_AXI_PROTOCOL_SG VISIBLE true
-set_parameter_property DMA_AXI_PROTOCOL_SG GROUP $group
+set_parameter_property DMA_AXI_PROTOCOL_SG GROUP "Scatter-Gather"
 
 add_parameter DMA_DATA_WIDTH_SG INTEGER 64
 set_parameter_property DMA_DATA_WIDTH_SG DISPLAY_NAME "Bus Width"
 set_parameter_property DMA_DATA_WIDTH_SG UNITS Bits
 set_parameter_property DMA_DATA_WIDTH_SG HDL_PARAMETER true
 set_parameter_property DMA_DATA_WIDTH_SG ALLOWED_RANGES {64}
 set_parameter_property DMA_DATA_WIDTH_SG VISIBLE true
-set_parameter_property DMA_DATA_WIDTH_SG GROUP $group
+set_parameter_property DMA_DATA_WIDTH_SG GROUP "Scatter-Gather"
 
 set group "Features"
 
@@ -302,6 +311,7 @@ proc axi_dmac_validate {} {
   set auto_clk [get_parameter_value AUTO_ASYNC_CLK]
   set type_src [get_parameter_value DMA_TYPE_SRC]
   set type_dest [get_parameter_value DMA_TYPE_DEST]
+  set sync_start [get_parameter_value SYNC_TRANSFER_START]
 
   set max_burst 32768
 
@@ -376,6 +386,9 @@ proc axi_dmac_validate {} {
 
   set_parameter_property MAX_BYTES_PER_BURST ALLOWED_RANGES "1:$max_burst"
 
+  set_parameter_property AXIS_TUSER_SYNC ENABLED [expr {$type_src == 1 && $sync_start == 1} ? true : false]
+  set_parameter_property AXIS_TUSER_SYNC VISIBLE [expr {$type_src == 1} ? true : false]
+
   set cache_coherent [get_parameter_value CACHE_COHERENT]
   set axcache_auto [get_parameter_value AXI_AXCACHE_AUTO]
   set axprot_auto [get_parameter_value AXI_AXPROT_AUTO]
@@ -472,9 +485,10 @@ ad_interface clock   fifo_wr_clk       input   1                       clk
 ad_interface signal  fifo_wr_en        input   1                       valid
 ad_interface signal  fifo_wr_din       input   DMA_DATA_WIDTH_SRC      data
 ad_interface signal  fifo_wr_overflow  output  1                       ovf
-ad_interface signal  fifo_wr_sync      input   1                       sync
 ad_interface signal  fifo_wr_xfer_req  output  1                       xfer_req
 
+ad_interface signal  sync              input   1                       sync
+
 proc add_axi_master_interface {axi_type port suffix} {
   add_interface $port $axi_type start
   set_interface_property $port associatedClock ${port}_clock
@@ -630,19 +644,19 @@ proc axi_dmac_elaborate {} {
   if {[get_parameter_value DMA_TYPE_DEST] != 2} {
     lappend disabled_intfs \
       if_fifo_rd_clk if_fifo_rd_en if_fifo_rd_valid if_fifo_rd_dout \
-	  if_fifo_rd_underflow if_fifo_rd_xfer_req
+      if_fifo_rd_underflow if_fifo_rd_xfer_req
   }
 
   if {[get_parameter_value DMA_TYPE_SRC] != 2} {
     lappend disabled_intfs \
       if_fifo_wr_clk if_fifo_wr_en if_fifo_wr_din if_fifo_wr_overflow \
-      if_fifo_wr_sync if_fifo_wr_xfer_req
+      if_fifo_wr_xfer_req
   }
 
-  if {[get_parameter_value DMA_TYPE_SRC] == 2 &&
-      [get_parameter_value SYNC_TRANSFER_START] == 0} {
-    set_port_property fifo_wr_sync termination true
-    set_port_property fifo_wr_sync termination_value 1
+  if {[get_parameter_value SYNC_TRANSFER_START] == 0 || \
+     ([get_parameter_value DMA_TYPE_SRC] == 1 && \
+      [get_parameter_value AXIS_TUSER_SYNC] == 1)} {
+    lappend disabled_intfs if_sync
   }
 
   if {[get_parameter_value ENABLE_DIAGNOSTICS_IF] != 1} {