xilinx/ad_data_in.v: Add SDR support

analogdevicesinc · Sep 7, 2023 · aa11f43 · aa11f43
1 parent c8a131e
commit aa11f43
Showing 1 changed file with 33 additions and 27 deletions.
diff --git a/library/xilinx/common/ad_data_in.v b/library/xilinx/common/ad_data_in.v
@@ -38,6 +38,7 @@
 module ad_data_in #(
   parameter   SINGLE_ENDED = 0,
   parameter   FPGA_TECHNOLOGY = 0,
+  parameter   DDR_SDR_N = 1,
   parameter   IDDR_CLK_EDGE ="SAME_EDGE",
   // for 7 series devices
   parameter   IDELAY_TYPE = "VAR_LOAD",
@@ -158,7 +159,7 @@ module ad_data_in #(
   end
   endgenerate
 
-  // receive data interface, ibuf -> idelay -> iddr
+  // receive data interface, ibuf -> idelay -> iddr(if enabled)
 
   // ibuf
 
@@ -244,35 +245,40 @@ module ad_data_in #(
   end
   endgenerate
 
-  // iddr
+  // DDR or SDR
 
   generate
-  if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
-    IDDRE1 #(
-      .DDR_CLK_EDGE (IDDR_CLK_EDGE)
-    ) i_rx_data_iddr (
-      .R (1'b0),
-      .C (rx_clk),
-      .CB (~rx_clk),
-      .D (rx_data_idelay_s),
-      .Q1 (rx_data_p),
-      .Q2 (rx_data_n));
-  end
-  endgenerate
+    if (DDR_SDR_N == 1'b1) begin
+      // iddr
+      if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
+        IDDRE1 #(
+          .DDR_CLK_EDGE (IDDR_CLK_EDGE)
+        ) i_rx_data_iddr (
+          .R (1'b0),
+          .C (rx_clk),
+          .CB (~rx_clk),
+          .D (rx_data_idelay_s),
+          .Q1 (rx_data_p),
+          .Q2 (rx_data_n));
+      end
 
-  generate
-  if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
-    IDDR #(
-      .DDR_CLK_EDGE (IDDR_CLK_EDGE)
-    ) i_rx_data_iddr (
-      .CE (1'b1),
-      .R (1'b0),
-      .S (1'b0),
-      .C (rx_clk),
-      .D (rx_data_idelay_s),
-      .Q1 (rx_data_p),
-      .Q2 (rx_data_n));
-  end
+      if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
+        IDDR #(
+          .DDR_CLK_EDGE (IDDR_CLK_EDGE)
+        ) i_rx_data_iddr (
+          .CE (1'b1),
+          .R (1'b0),
+          .S (1'b0),
+          .C (rx_clk),
+          .D (rx_data_idelay_s),
+          .Q1 (rx_data_p),
+          .Q2 (rx_data_n));
+      end
+    // sdr
+    end else begin
+      assign rx_data_p = rx_data_idelay_s;
+      assign rx_data_n = 1'b0;
+    end
   endgenerate
 
 endmodule